The Research Of System Verilog Assertion-Based Verification Method For Nand Flash Controller

Simulation is the most complex and time-consuming section in the SoC design flow,about 70% to 80% of the chip design cycle. The workload of verification to design is several times, along with the urgency of Time -to-Market demand, functional verification has become the largest bottleneck in modern design of SoC.The traditional method of functional verification can be observed poorly, traceability is not strong, which lead to locate problems slowly, the cycle of verification is long,the reuse of verification environment is poor and the level of automation is lower.To solve these problems, this paper researched the SVA (SystemVerilog Assertion)-Based functional verification method in the development of SoC chip SEP0718.The method uses the advantages of the assertions technology to make up for the weekness of dynamic simulation. A generic assertion IP (Intellectual Property) was developed according to features of the NFC (Nand Flash Controller) of SEP0718,and this assertion IP was used for the two different platforms:BFM (Bus Functional Model) module-level verification platform and the BFM SoC-level verification platform.Some verification components were developed according to the specificity of Nand Flash read and write operations,such as:Random-Stimulus Generator which can produce a variety of read and write operations for NFC,Scoreboard,Functional coverage module. Constraint Randomized Verification was realized by Random-Stimulus Generator; The development of Scoreboard improve the automation of the verification platform; Coverage Driven Verification was used by coverage of functional module,which can guide the direction of the next step of verification so as to promote the work of verification constantly advancing. A verification platform of NFC based on SVA was build by using these validation components. The complete verification for NFC was done by using of the module-level verification platform,Then, the BFM SoC-level verification platform was built, based on the platform of module level and the NFC SoC-level verification was completed. Verification results show that, the functional coverage and assertion coverage of NFC BFM module-level and SoC level verification all reached 100%. Also the project proved that,SVA-based verification can combine the three elements of the environment:the produce of stimulus,scoreboard,coverage, exploiting the advantages of the three elements to the maximum. And the automation of verification platform was improved, the verification process can be observed and can be traced easily, the debugging process was simplified, the heavy work to validate staff was reduced, the design development cycle was reduced effectively. As a result, it guarantees the success of the design of chip.