The Research And Implement Of The JESD204B Interface

With the rapid development of electronic technology,high-speed AD sampling technology has been increasingly applied in communications,industrial instrumentation,imaging equipment and other large data acquisition system,so that it is very necessary to study the interface technology of data converter.The improvement of the sampling rate and the resolution of the converter also puts forward higher requirements for the interface,more efficient interface requirement has become increasingly urgent.In solving the problem of data converter interface,we need to meet the requirements of interface rate,but also as much as possible to simplify the design.Traditional sampling data using multi-channels to transmit the data in parallel way,it causes the inter-code synchronization and crosstalk effects,and PCB routing is complex.It is difficult to meet the multi-channels,high bandwidth,miniaturization of digital transmission terminal needs.At present,analog-to-digital converters(ADCs)are experiencing transition from parallel LVDS(low-voltage differential signaling)and CMOS digital interfaces to high-speed serial interfaces.CMOS and LVDS have the problems of slow transmission speed and high complexity in high speed converters.In order to achieve high-speed and smaller size requirements,JEDEC issued a new agreement JESD204 in 2006,followed by the introduction of JESD204 A and JESD204 B,it has gradually become the new standards of serial data conversion and logic device interconnection in the industry.It also brings a new design assistance option for the high-speed data acquisition engineers.JESD204B interface is a high-speed serial interface,which makes full use of high-speed bandwidth advantages of Ser Des,and wiring is simple.The protocol is divided into transport layer,link layer,physical layer.The transport layer is responsible for data frame mapping,and support for a variety of mapping according to the protocol.Interface also provides optional scrambling / descrambling operations;link layer is mainly responsible for the synchronization,code,character replacement and other functions;the physical layer is responsible for serial and parallel conversion of data.It supports deterministic delays and more flexible clocks to achieve the purpose of delay control,so as to facilitate synchronization between different lines.204 B interface of the protocol has reached the transmission speed of 12.5Gbps,and it has gradually become the standard of high-speed data converters.The maximum transfer rate of the interface designed in this paper depends on the maximum transmission rate of Ser Des.Ser Des supports up to 15 Gbps.The sampling rate of the converter can be selected flexibly according to the mapping mode and sampling mode.The maximum sampling rate is 737.28 MHz.This paper mainly introduces several different interface of data converters,CMOS,LVDS,and the new interface of JESD204 B,compares the advantages and disadvantages of each kind of interface.It mainly analyzes the principle and implementation of the interface of204 B,introduces the principle and the realization of data transmission for each layer and the key technology of the 204 B interface,design the interface based on the protocol,the design scheme is in strict accordance with the protocol requirements and achieves the rate agreement requirements,it uses the Verilog language to realize the interface design,and analyzes and reflects the simulation of the interface.