A Design Of Serial Data Interface Based On JESD204B Protocol

With the development of data quantity in various fields,more and more applications require high-speed and high-precision AD / DA converters,which promotes the rapid development of related technologies,but the power consumption and area of device packaging also increase.Due to the above factors,the traditional CMOS,LVDS and other interfaces are more and more difficult to adapt to today's needs,so the new high-speed data transmission interface is now a focus of high-speed converter applications.After the research and analysis of the layered structure of the protocol,this paper defines the specific function of each layer,and designs the functional modules according to the standard.On this basis,this paper designs a high-speed serial data transmission interface circuit based on JESD204 b protocol for the target device with dual channel,16 bit resolution and 250 Msps sampling rate,and realizes the deterministic delay of subclass 2 specified in the protocol.In the design,a 32-bit parallel scrambler with bypass selection function is derived and implemented,which can be selected according to the actual use.Based on the analysis of the resource occupancy and stability of the traditional implementation methods,this paper also designs and implements an improved 8B / 10 B encoding module combining LUT method and logic operation method.Compared with the traditional method,this module not only can save on-chip logic resources and storage space,but also has k-code error detection function.This paper uses Verilog HDL language to designs modules based on quartus prime which is Altera's FPGA development tool,and carries out functional simulation verification in Quartus + Modelsim joint debugging platform.Through the observation and analysis of the simulation results,it is proved that the function of the interface module is correct.Finally,based on the Arria 10 FPGA development board kit of Altera company and communication with ADRV9009 which is RF transceiver chip,After verification,it can send and receive data correctly,so it is verified that the interface module can achieve the expected parameters.