Design And Implementation Of JESD204B High-speed Serial Interface Based On UVM

When the fifth generation of mobile communication technology has become a global focus,and high speed DAC and ADC sampling rate,transmission speed and resolution is 5G communication technology in high data rate,high performance target of the key factors,such as solid state technology association launched JESD204B high-speed data transmission interface can solve the transmission speed of DAC/ADC chip,has a higher sampling rate,high performance and low power design needs.In order to improve the transmission speed of data with deterministic delay and increase the bandwidth,and realize the fast and accurate data,an 8GS/s 14-bit DAC chip based on 40nm CMOS process digital standard cell library adopts the design of JESD204B receiver to realize the data transmission of high-speed interface.The JESD204B receiver interface realizes 16-bit data output per channel,the working clock is 500MHz,and the receiver layout area is 2.06mm2.The main tasks are as follows:(1)JESD204B receiver high-speed interface design and implementation,including the definition of the port,module composition division,working principle and Verilog code writing and implementation,and the receiver top-level circuit,data transmission circuit design described.(2)The design of JESD204B receiver interface was built with UVM simulation environment,and the environment was configured.The incentive was transferred to the JESD204B receiver design through the control interface.The realized functions were simulated and verified.(3)Carry out digital back-end layout design for JESD204B receiver design and other digital circuits,including logic synthesis and layout design,pass timing and physical verification,and finally flow chip.Then,the application verification of the 8GS/s 14bit DAC chip was carried out.In the test system,it was sent to the DAC chip through the eight-channel JESD204B interface,and the highest transmission rate of each channel was 10Gbps.The test results show that the function of the design meets the requirements,and the transmission rate and operating frequency can meet the protocol specification.The JESD204B interface,which is suitable for high-speed data acquisition and transmission,can achieve better transmission quality and higher transmission rate.Meanwhile,it can also reduce the package size and promote the development of high-speed interface technology in China,so as to ensure that DAC/ADC chips can be improved in the direction of higher precision and higher sampling rate.Therefore,this thesis adopts JESD204B interface design and applies it to the high-speed and high-precision DAC chip of 5G high-performance base station,which can reduce the cost of layout,wiring and system design as a whole,as well as the power consumption.