The Research Of FPGA IP Core Reinforcement Technology Based On Aerospace

With the increasing amount of data processed by spacecraft,SRAM-based FPGA is used as the first choice for satellite-carried devices by more and more aerospace departments. Because of its high parallel processing speed, reconfigurable feature and easy to be realized, the SRAM-based FPGA becomes one of the most popular devices in aviation applications. However, in the outer space environment, the SRAM-based FPGAs are highly susceptible to space radiation and that result in a single event upset, which would lead to system error further. Therefore, the aerospace reinforcing technology that aims to ensure the high reliability of data, gradually attracts wide attention from academia.In this thesis, several common types of fault in aviation devices are introduced and compared with each other. Due to the flipping of data bits,system becomes unstable, but the existing reinforcement methods (such as triple-mode redundancy) mostly deal with the single-bit flip fault,ignoring the need for solving two-bit flip fault in high-reliability system.Therefore, according to the deep research of XOR relationship between data, a new reinforcement technique of coding and decoding based on five-bit XOR network topology is proposed in this thesis. The contribution of this thesis includes two aspects:(1)A method based on five-bit XOR mesh error detection and correction is proposed. The reinforcing method establishes an XOR logical relationship between data in the coding module, and in the decoding module, the same relationship is used for fault detection and error correction. This thesis expounds both principle analysis and theoretical derivation, and the correctness of single and double bit flip fault is verified as well by circuit design, simulation experiment and FPGA embedded platform test. The experimental results show that,compared with other methods, the proposed method can not only achieve error detection and error correction of single and double particle inversion,but also can be applied to many complicated environments. In addition,the reinforcement method can also detect 3-bit and 4-bit errors, which can further enhance the system's reliability.(2) A random embedded verification environment combining hardware based on FPGA with software based on Matlab is presented in this thesis. As for the hardware, the embedded verification platform takes Microblaze as the core, and other IP core as peripherals. The software programming is realized by MATLAB, such as the random data and fault generated by Matlab and sent to the FPGA platform through serial port,the output result of FPGA analyzed automatically by Matlab and so on. In general, the verification system uses the fault injection module to simulate the single / double bit rollover failure caused by radiation in the outer space, and then practically verify the feasibility of the reinforcement method by actual test on the FPGA embedded platform. It can be shown from the experiments that the verification environment can not only carry on the real-time contrast analysis to the DUT (Design Under Test), but also can greatly improve the reliability of the system verification.