| X ray polarization detection experiment is an important method for studying astrophysics.The successful development of a micro-pattern gas pixel detector based on the photoelectric effect makes high-sensitivity polarization detection possible,opening a new window for X-ray polarization detection.The photoelectron track pixel detector is the most commonly used two-dimensional position detector of this type of detector.It has very low noise and high resolution.However,as the size of the pixel array continues to increase,the readout electronics of the pixel chip is becoming more and more complex,and it already includes functional modules such as pixel array controlling,microcontrollers,dedicated data processing units,and high-speed transmission interfaces.With the development of semiconductor manufacturing technology and integrated circuit design technology,it has become easier for the pixel chip readout electronics system to be made into a SOC(System On Chip)chip.The electronic system made of SOC chip is beneficial to reduce system power consumption and payload weight for the X-ray polarization detection experimental system on the satellite.However,the processing efficiency of general-purpose processors is low,and the dedicated data processing unit and digital interface are not flexible.In order to improve the flexibility and efficiency of the pixel chip read-out electronic on SOCs,an embedded FPGA(eFPGA)core,named "FLEXY",is proposed for the pixel chip.The major works and innovations include the following aspects:1.Verilog hardware description language is used to design the scalable eFPGA core.and model the basic elements of eFPGA’s programmable logic block,connection block,switch block,configuration circuit.The eFPGA core has the same functions as the traditional FPGA,and because of the use of RTL-level Verilog language modeling that has nothing to do with the manufacturing process,it can be easily transplanted to different chip manufacturing processes.This thesis uses an ASIC-based automated digital IC design process to design the back-end of the chip.Compared with the traditional full-customized solution,the layout design work is reduced and the development period is shortened,2.For the eFPGA core,a dedicated bitstream generation software VTB(Verilog To Bitsream)is designed based on the open source FPGA placement and routing tool VTR.The software can complete processes such as logic synthesis,process mapping,placement and routing,and bitstream generation,and can meet the application development requirements of the eFPGA core.3.In the space radiation environment,semiconductor devices are susceptible to radiation effects,so this article designs an SEU radiation hardening circuit for the configuration register in the eFPGA core.This circuit adds an error detection and recovery circuit to the traditional three-mode redundancy circuit,so that the circuit can recover the upset register without the participation of an external refresh circuit,which enhances the radiation harden of the eFPGA core.The results of functional simulation and FPGA prototype verification show that the proposed eFPGA core and bitstream generation software can realize certain digital circuit applications.In order to evaluate the eFPGA core,a prototypical chip that has 10×10 CLBs,800 four-input look-up tables,800 programmable flip-flops,is implemented with GSMC 0.13 um process.The final area of the chip is 2.8×2.8mm2 and the equivalent number of logical gates is about one million. |
