Radiation Reliability Of Novel MOSFET And TFET Devices

Silicon-on-insulator?SOI?technology is advantageous over traditional bulk silicon CMOS primarily because of its insusceptibility from the latch-up effect of four layers with p-n-p-n structure as a result of the complete dielectric isolation of individual transistors.And SOI devices have been developed for radiation-hardened military and space applications for many years.However,ionizing radiation generally degrades the electrical performance of MOS devices by creating interface traps and oxide-trapped charge in gate dielectric.Introducing buried oxide layers increases the susceptibility of SOI devices compared with bulk transistors to Total Ionizing Dose?TID?radiation damage in deep submicron processes.Meanwhile,in the deep submicron technologies,the gate oxide becomes thinner and less sensitive to TID irradiation.And the total ionizing dose responses of MOS devices is mainly the trapped charge in the shallow trench isolation oxide,which is becoming the dominant isolation technology for commercial deep submicron CMOS porcess.Thus,numerous experiments,simulation methods and mechanism analysis for these special phenomenon should be conducted.In addition,further research showed that tolerance to Single Event Effect?SEE?decreased with the technology downscaling,becoming critical in SOI device.And simulator has been proved as an effective approach to investigate the effect of SEE on device.Meanwhile,the majority of radiation effects on the electrical characteristics of devices are usually considered on MOSFETs.However,very few studies on the TID effect of TFETs have been conducted,and heretofore,there is no publication about the damage mechanism of Single Event Transient?SET?of TFET.Nevertheless,reducing the on-current of the memory cell transistors reduces not only the speed of the read operation,but also increases the sensitivity versus radiation induced charge and weakens the Single Event Upset?SEU?tolerance of TFET-circuits.Thus,it makes sense to study the SET characteristics of TFETs.The radiation reliability of novel field-effect transistors with buried oxide devices and 65nm bulk silicon MOSFET are researched and the main contribution of this paper is as follows.1.The impact of total dose on H-gate NMOSFETs in a partially-depleted SOI technology is researched.By analyzing the data,the threshold voltage,subthreshold swing,transconductance,and output conductance show obvious degradation under TID effect.For the body-grounded device,the negative shift quantity of threshold voltage increases after irradiation.However,if the irradiation bias state of devices was floated body,the threshold voltage shows a negative shift at first,then turns to negative shift when irradiation dose is not high?200³00 krad?Si??,and the phenomenon is called“rebound”.The positive charges in buried oxide layer induced by irradiation raise the potential.Electrons are attracted to move nearby the Si/SiO₂ interface.It weakens the formation of channel,which cause the threshold to shift toward a positive direction.2.The influence of dose rate effects on the PDSOI device is also discussed.The research results show that the threshold voltage shift is more significant in low dose rate condition,even for the low dose of 100 krad?Si?.Experimental data also shows that the shift in the saturation current is larger at high dose rate than that at low dose rate.The above phenomenon are due to the increasing interface-state density with decreasing irradiation dose rate.Meanwhile,the scattering effect of the interface state on the electrons in the channel will lead to carrier mobility degradation.In addition,the body current and transconductance of the back-gate have enhanced low dose rate sensitivity when the irradiation condition is under OFF-bias.A double transconductance peak is observed at300krad?Si?under high dose rate condition.3.The total dose effect of 65 nm MOSFET is also studied with industrial Cobalt 60?-ray irradiation facility.On one hand,after irradiation,the commercial 65 nm technology,especially the device with STI structure,showed degradation mainly in the subthreshold current and off-state current,whose degradation behaviour is gradually slow down with increasing W/L ratio.For a constant channel length,more variability is observed for narrow width devices compared to wider devices before and after irradiation.On the other hand,with the n doping LDD structure with drain and p+halo-doping in the channel near source,the radiation tolerance of device can be enhanced.And the degradation of threshold voltage and transfer characteristic of parasitic transistor is decreased after irradiation.Meanwhile,reduced subthreshold current and off-state current and improved threshold voltage are observed,and the output resistance is seven times larger than that of the MOSFET without halo-doping.A remarkable characteristics enhancement of the asymmetrical doping structure can be obtained.4.The Single Event Upset of 6T SRAM based on 3D structure of H-gate Partially Depleted Silicon-on-Insulator device is researched.On one hand,the variety of stored voltage is generated with the incidence of different heavy ion.The parameters of upset threshold and maximum static power are obtained,which coincide with the data of experiment.And the simulation results verify the accuracy of the model structure.On the other hand,by using the capacitors which are connected to the sensitive nodes,the cell of SEU radiation-hardened is realized,and the value of capacitor is acquired?the capacitor is 12.8fF as LET=100 MeV?cm²/mg?,which can be used in the 6T SRAM consisting of the device dimension presented in this paper.5.The comparison of Single Event effect between partially-depleted SOI and fully-depleted SOI with 0.2?m CMOS technology is researched.By using circuit simulation model of ISE TCAD and HSPICE,the 6T SRAMs with the above two devices have been investigated,respectively.The effect of single event upset caused by the heavy ion impact with different linear energy transfer characteristic is analyzed.And the simulated results show that the resistance SEU ability of FDSOI device is much better than that of PDSOI device.For FDSOI SRAM,the upset threshold belongs to the range from 118 to 119 MeV?cm²/mg and the critical charge belongs to the range from 1.2044×10^-13 to 1.2084×10^-1313 C.6.The DC characteristics and RF/anology performance comparisons of L-shaped channel TFET?LTFET?and U-shaped channel TFET?UTFET?are investigated by using Sentaurus TCAD tool.The simulation results reveal that the better electrical performance LTFET provides due to it has the much smaller C_gd than UTFET.And the calculated results demonstrate LTFET is more optimization for inverter circuit design in the novel generation transistors.Meanwhile,the SEE on LTFET with buried oxide layer is firstly investigated in this paper.The simulation results show that the obvious different radiation damage between MOSFET and TFET with the different carrier transport mechanisms.The transient current induced by heavy ion striking much larger than the on-state current for LTFET.And the TFET device is more sensitivity to SEE than MOS device.By analyzing the contributions of electrostatic potential,electric field and energy,the impact ionization rate and the Shockley–Read–Hall?SRH?recombination,the physical mechanism of SEE on LTFET is obtained.Meanwhile,the paper also gives out the sensitive area of LTFET in SEE,which is the body region below source region.