Research Of Reliability Design Of On-board Switching Equipment

On-board switching (OBS) equipment, different from terrestrial network nodes, aims to cope with the bad space physical environment and serious interference of energetic charged-particles. Satellite manufacturing and launching would cost much, and furthermore, the difficulty of replacement or reconfiguration of the on-board devices after launch is also high. Thus, reliability design of the OBS equipment must be researched and achieved at the early stage. Anyhow OBS equipment is an important component of future space/ terrestrial network infrastructure, but how to guarantee system's reliability to normal work in space radiation environment is a challenging issue.Using shielding material is a natural solution to mitigate radiation. Redundancy, as the conventional technique of reliability design, is applicable to on-board devices as well. With the FPGA's applications in space, the chip's immunity to Single-Event Upsets (SEU) in itself is getting higher and higher. However, because of some factors, using commercial off-the-shelf (COTS) is more sensible.In this thesis, an OBS system architecture has been developed. The utilization of fault-tolerant module ensures the system's performance and reliability. Meanwhile, according to the SOC design methodology, a multi-level fault-tolerant mechanism has been researched. First, at the system-level, dual-module redundancy scheme is adopted to the Control module and switch module, while triple module redundancy (TMR) strategy is adopted to the fault-tolerant module. Secondly, at the module-level, Hamming coding and TMR are integrated so as to enhance the anti-SEU ability of memory such as FLASH and SRAM. Third, to mitigate the FPGA's SEU effects, fault-tolerant state machines, I / O signals and configuration bits have been taken into account at the chip-level.Full mitigation of an FPGA design using TMR, however, is costly in resource utilization and causing a significant increase in power consumption. A wise choice is the MSBPR scheme as mentioned in this thesis. This scheme is based on the prediction of SEU rates and applies TMR at different levels. When the rate increases, the critical configuration bits must be mitigated at first.On the basis of the above, the author participated in the design of an on-board ATM switch. Modeling and analysis have been done to the system's reliability. It should be helpful to the future's realization of Commercial products.