Resistance To Single Event Upset Of Sram-based Fpga Test System Research And Design

Compared to other chips used under radiation environment, SRAM-based FPGA has an advantage of large integrated scale, low cost and re-configuration after facility launching. However, this structure is more easily influenced by single event effect. Because of low research level of our state in this field, it becomes a urgent problem to be solved that a SEU-hardening and test and efficient evaluation system should come into use.In order not to be restricted by other countries, and in order to get full application of SRAM-based FPGA, a SEU-hardening and testing system for SRAM-based FPGA is built after lots of study being conducted and several methods tested. XCV300 of Xilinx is used to conduct fault simulation by this system. According to SEU interface of radiation test under certain condition, function error interface can be estimated. The comparison between simulation and radiation is used to estimate this system.This study sums up principle of SEU in SRAM-based FPGA, SEU-hardening and test methods. It also gives a design of a testing system that can SEU-harden FPGA whit function of simulation and radiation, containing PC control software, system test PCB and other relative circuit structure. What's more, this system is used to simulate SEU, the result is compared with radiation tests and the comparison is analyzed.The system designed in the study is more convenient to remote control, configure and update, thus make it easy to test and lower the cost of tests. The study focuses more on consummating the function of simulation SEU. To SRAM-based FPGA, SEU interface has nothing to do with circuits, but influenced by parameter of injecting particle, such as dose rate, angle of incidence and injecting area. Therefore, the approximate function error interface of different circuits can be reached just by simulation SEU of required situation. This benefits the SRAM-based FPGA designing under radiation environment.