IP Core Design And Simulation Based On PCIe Bus

With the development of the modern processor technology,using high speed difference bus instead of parallel bus in the field of interconnection is pushed by the general trend of events.PCIe bus use high speed difference bus,and use point-topoint connect way,so each PCIe chain only can have two devices.It makes PCIe bus' s topological structure different from traditional bus.PCI Express bus is proposed by Intel,its purpose is to better meet the requirements of data transmission to replace previous computer system bus transmission interface.In order to meet the different needs of the business,the interface modes to choose from,including 1x,2x,4x,8x and 16 x,etc.In the PCI protocol,the size of the configuration space is 256 bytes,this far from satisfaction of PCIe bus address space,so the PCIe protocol configuration space expands to 4096 bytes.In this protocol,top 256 bytes are same to the PCI configuration space,the remaining space space is only for PCIe and only through ECAM the access mechanism to carry on the corresponding configuration.In PCIe configuration space,PCI has 4M space address that can compatible with PCI mechanism.If PCI bus devices access more than 256 bytes,it only can read back all 0.The purpose is to convince PCIe access mechanism in order to avoid unnecessary access chaos.Based on known PCIe bus protocol,this essay realized PCIe bus IP core design,one the most significant design is the design of transaction layer,data link layer,application interface layer and peripheral configuration space.About physical layer,due to the mature technology in China,so use existing module.This essay introduces assembly and disassembly of data,structure of data package head,sending and receiving,as well as request and completed in transaction layer.DLLP,ACK/NAK protocol,TC/VC arbitration and flow control in data link layer.Detail of sending and receiving logic in physical layer.DMA carry and data packaging in application interface layer.In the case of meeting PCIe agreement,realizing the optimization of adjustment and meet the requirements of the design.This essay is divided into theoretical part and validation parts.In theoretical part mainly describe in detail the development history and the origin of the PCI Express,protocol layers in the working principle and method of implementation.In validation part,by building Debussy hardware circuits,we can know the framework of IP core from outer to inner,and we can understand various modules' underlying structure.By writing testbench test platform,we can see timing sequence and hardware code is true or false.In practical ways,the main function of testbench are test root complex's topological structure and endpoint's different read/write ways and data sending and receiving.