The UVM-based Verification Method Of Data Transmission Order In PCIe Bus Interface

As the level of semiconductor technology continues to advance,the scale of digital circuits continues to expand,and the functions of system-on-chip are increasingly diverse.In order to design a chip that meets the user's needs and cost savings,chip developers need to successfully tap out and market the chip in a short period of time.One of the keys to the success of taping out is the complete functional verification of digital circuit design.The increasingly shortened iteration cycle of the chip and the increasingly complex functions of the system make chip verification more challenging.In order to ensure the efficiency,completeness and reusability of verification,the language and EDA tools used for verification are constantly evolving.At present,System Verilog has become the mainstream verification language.Based on the System Verilog language,UVM methodology provides a mature framework for verification,which greatly increases the reusability and represents the development direction of verification methodology.PCIe,a high-performance and high-bandwidth general-purpose I/O interconnect bus,is one of the local buses commonly used in current SOC.It inherits from the PCI bus and expands a series of new functions,such as point-to-point interconnects,the data transmission mode of the packets,virtual path and flow control.The research object of this paper is a PCIe bus interface customizable IP that I am involved in the development of in the internship company.The IP,responsible for data transmission between the CPU and different system devices,manages numerous system devices,such as USB,SATA,external graphics cards,etc.It is difficult to design and used in many projects of the company.The ordering,the order of data transmission,is the key to ensure the integrity of the system data and an effective method to prevent system deadlock.In computer systems,many software programs require computers to perform specific events in a specific order.If the instructions of a software program cannot be executed in the expected order in the hardware circuit,the program will have many unknown errors.The data transfer ordering rule defined in the PCIe specification rearrange certain events without affecting the device operation program in order to achieve the purpose of optimizing system performance,and strictly enforce the sequence of data affecting the operation.Reasonable arrangement of the ordering of data access is crucial for bus design,especially bus interface design,and is a key issue for verification personnel in the verification process.This topic uses a UVM-based verification method to fully verify the data transfer ordering of the bus interface.My work in this project mainly includes: familiar with IP design specifications and system structure,understand the functions of each sub-module on the two data paths of DMA and HOST,and focus on the data transfer order relationship between them;Participate in the establishment of a verification platform for all functions of the IP based on the UVM,which is mainly responsible for the creation and connection of Interface UVC and and the addition of components in Module UVC to predicte and compare the correctness of the ordering function;Responsible for the verification of the ordering function,formulate a complete verification plan with all functional verification points and specific verification methods according to the PCIe ordering rule;write test cases according to the verification plan.And different test cases are used to verify different aspects of the function;Use the VCS tool perform multiple simulations,and collect the coverage results after the simulation was successful;achieve the verification goal of 100% functional coverage and code coverage after repeated simulations,and the verification was completed.This topic makes full use of the features of System Verilog language and UVM methodology to ensure the configurability and reusability of the verification platform and test cases,so that they can be reused in different projects with minor changes or different parameters.It is convenient for postperson maintenance,shortening the verification cycle,ensuring the completeness of verification and improving the verification efficiency in future projects.This paper also provides a feasible and complete verification method for the verification of the "ordering" function in the bus protocol such as PCIe,which can be used as reference for the industry.