PCIe Interface Research In 4Gbps FC Network Communication

With the rapid increase of FC network communication,the system need to deal with the amount of data analysis also constantly improve,with 2.5 G the baud rate of transmission of PCIe interface cannot meet the demand of data transmission.Based on FC network transmission of data in real-time,reliable,and recommend suite needs,select a one-way transfer rate of 5 G PCIe 2.0 standard baud rate,with the method of design and validation,the PCIe interface were studied.This paper from the perspective of demand,in the FC network communication related problems to solve,for later face higher data bandwidth theory basis provided for the problem.First of all,introduced the development status of this research,the paper overall architecture design,secondly,analyzed the FC protocol and FC network topology,through the data instance in the FC network research,clear PCIe interface in the FC network transmission function,after in-depth PCIe agreement,including the system architecture and PCIe architecture,complete the PCIe IP core design,summarizes the PCIe interface functions and configuration of space access method,finally build verification platform,complete the PCIe interface of function and the performance verification.PCIe protocol aiming at the physical layer,data link layer,transaction layer parsing,and elaborates the packet structure of different layer,design lay the foundation for subsequent PCIe interface.PCIe IP core was designed mainly from transmission layer,data link data,physical layer and power management module,and based on the function of the PCIe interface implement summary for the local interface module,interface module management,configuration registers extension interfaces message interface and power management.PCIe interface configuration space and related registers,and form the x86 processors and Power PC processor two cases of PCIe configure space for vist.For PCIe interface part of the function and performance verification,contains the PCIe related registers,speaking,reading and writing and reset verification,and traditional interrupts and MSI PCIe interface validation and PCIe four-to-one line performance verification.