A Design And Verification Of Gigabit Ethernet Chip Supporting PCIe

With the rapid development of AI,IOT,and computer data transmission,SOC integrated Ethernet interfaces are required to communicate with other devices and PCIe interfaces are required to provide high-speed interconnection.Therefore,gigabit Ethernet chips supporting PCIe are required.The PCIe Giga bit Ethernet chip provides Ethernet transceivers,power consumption management,and error detection.The Ethernet supports ieee 802.3U/AB/X,IEEE802.1Q,and remote wake up frame sending and receiving,and proactively receives and sends related data packets to PCS through the PCIe terminal and sends them to the upper-layer software.For the power management function,the device uses a timer built-in in the PCIe endpoint controller to idle PCIe links and put power supplies into D1 sleep state,reducing the power consumption of the PCIe and AXI buses.Between devices,enter a dormant state,when the PC driver can set the Ethernet control enter a dormant state,in this case,the PCIe power will enter D3 Hot state,at the same time,the internal data channels and Ethernet controller will enter a dormant state,until the sensei frame sensei hardware or software from a dormant state enter the running state,The design will send or receive power management enablement packets according to these two situations to wake up the PC or from hibernation to normal working state.In addition,when the Ethernet controller detects CRC errors or internal transient FIFO overflow errors,the errors will be reported to the upper driver for processing,and the software will deal with the corresponding errors to realize the function of error message detection.Therefore,the design will be divided into four parts: Ethernet controller and transceiver,PCIe controller and transceiver,AXIpcie bridge and configuration module composed of Cortex-M3,AHB bus matrix and EEPROM,wherein the Ethernet controller internal DMA controller,with a XI-pcie bridge to complete Ethernet packet and PCIe packet conversion,Implements data exchange between Ethernet and PCIe.In order to ensure the correctness of chip design functions,a reusable and reusable verification environment will be built by using the general verification methodology(UVM).The PCIe authentication component provides functions such as sending and receiving,traffic control,virtual cache,transaction sorting,and encoding and decoding at the application layer,transaction layer,data link layer,and physical layer.Data loopback verification excitation is designed to drive data from the external Ethernet verification component to the physical interface connected with the design and write into the cache.The data is transmitted to the PCIe interface through DMA and written into the memory in the external PCIe component.Enable DMA read operation to transfer DMA read data from internal memory of external PCIe components to the sending cache through the PCIe interface.The Designed Ethernet sending controller reads data from the sending cache and transmits it to external Ethernet components.The components receive data after confirming the correctness through address comparison and CRC check.After the circuit enters the low-power state by design excitation,the low-power state can be switched by software configuration.It can also realize switching of low power state by hardware itself,and verify that the design realizes data loopback function after switching between low power state and normal working state.The current verification coverage is 90.33%.The comprehensive coverage results and the simulation results of current data loopback,low-power state switch and magic packet remote wake up show that the main functions of the current chip Ethernet transceiver function and power management function have been realized and meet the protocol standards,and the error detection function needs to be verified.