Interface Design And Verification Based On PCIe Gen 4 And AXI Bus

PCI-Express is a serial high-speed computer expansion bus standard,referred to as PCIe.PCIe bus is widely used in personal computers,mobile phones and even workstations and servers.Nowadays,with the rapid development of storage technology and the rapid expansion of the amount of stored data,PCIe bus-based solid-state drives have gradually emerged,and have achieved an advantageous position in the SSD field with their superiority.Especially with enterprise-class SSDs used in data centers and servers,products with greater bandwidth and frequency are required to ensure their data rates.The PCIe4.0's tremendous increase in bandwidth and frequency makes this interface the preferred interface for enterprise SSDs.The PCIe protocol can be divided into a physical layer,a data link layer,and a transaction layer to coordinate the transmission of data packets.The data channel is dual-channel serial transmission through LVDS differential signals.The data in the protocol is transmitted through the format of the data packet.The data packet uses the128b/130 b encoding method to embed the clock.The flow control mechanism controls the data packet to be sent and received cooperatively in multiple data channels.The Nak/Ack mechanism ensures that the data packet is received correctly.The mechanism cooperates to ensure high bandwidth and high transmission efficiency of data.In this thesis,a high-speed PCIe interface applied to enterprise solid state drives(SSD)is designed according to functional requirements and the system is verified.This interface uses PCIe4.0 and the AXI bus specification based on AMBA3.0.Through this interface,high-speed data transmission between devices on the on-chip AXI bus and off-chip PCIe devices can be realized.This thesis first conducts a systematic research on the PCIe protocol,and understands the structure and functional characteristics of the PCIe interface through protocol learning,which provides a theoretical basis for the subsequent interface design and verification.Secondly,the interface structure is divided into two parts,PCIe IP core and peripheral circuit interface,to complete the design of the interface circuit.Peripheral circuit design is the top priority of this article.Peripheral circuits can enable the interface to meet the SOC's requirements for PCIe functions,optimize the interaction efficiency between the SOC and the PCIe interface,and sink some software operations to hardware processing to improve work efficiency.Finally,the interface is verified.The verification work is divided into two parts: UT verification and SOC verification to fully verify the function and performance of the interface.The verification process uses VIP(Verification IP)to help improve verification efficiency.Through verification and long-term regression testing,the interface function meets the requirements,and the interface is in PCIe x8 mode,the write performance bandwidth is 14.986GB/s,the read performance bandwidth is 14.719GB/s,and the performance meets the design requirements.