Design Verification Testbench Of SPI Interface IP Core Based On UVM

With the fierce improvement of Integrated Circuit scale and complexity, the hardness of verification and workload is increasing respectively. Generally, verification time of SoC (System on Chip) occupies almost over 70% of the IC development effort period. To build a test bench, applying traditional verification technology needs to cost much time. And even, the traditional verification methodology can not satisfy the requirement of IC design. Therefore, it has been a major issue in the field of IC verification to improve the efficiency and quality of verification.This thesis adopts the latest Universal Verification Methodology UVM to improve the speed and efficiency of verification. Article mainly introduces the basic theory of verification technology and UVM verification methodology, and the architecture of test bench including the structure and function of main components UVC is thoroughly researched. Then, some important mechanism will be analysed next. The most important advantage of SystemVeriog language is that it can improve the level of abstraction and reusability of test bench, meeting the requirements of the verification for language function. UVM methodology takes full advantages of the features of verification language, based on the unique characters of SystemVerilog language, such asencapsulation, inheritance, polymorphism, constraint and functional coverage.SPI (Serial Peripheral Interface) technology is a kind of communication bus which is high-speed, full-duplex and synchronous. It is widely applied to be integrated in the chip because of its features, which is simple and easy to use and even can save space for PCB. Some functional verification points are extracted on the basis of deep analysis of working principle of SPI interface IP core in the engineering practice. In the VCS environment of Synopsys, a test bench that can be used in the structure of SPI interface IP core is designed using UVM methodology and System Verilog language. It implements the functional verification of the working sequence of SPI interface IP core, data integrity, register access. And it completes the statistics of the functional coverage and code coverage. It has the characteristics of hierarchy and reusability, and greatly improves the efficiency of verification.