Audio Decoder Clock Jitter Reduction Circuit Base On FPGA

With the extensive application of large scale integrated circuit，Our lives become moreand more intelligent, miniaturized. The world’s leading power are used in motors, and digitalsystems, the main energy are used in the time on. Stability of the system clock directly affectsthe overall performance of electronic systems, therefore the clock circuit in the heart of adigital system.With the popularity of digital technology, digital audio has crept into our lives; Today, theold-fashioned tape recorder has been hard to find, replaced by a more compact MP3, audiointo the digital age has been. In the now popular digital decoding system, A/D and D/Achip sampling frequency higher and higher, faster and faster transfer rates, Any time on thedigital system errors are likely to impact on overall system performance, Time base jitterperformance of digital systems has become a constraining factor, Reduce system jitter is thebest digital audio decoding an important part of the design.For professional digital audio systems, When a performance-based system enables a betteroverall system performance improvement reborn. Why clock jitter has so much influence ondigital audio system? That is because the clock jitter can lead to digital audio distortion,restricting digital audio system to further improve signal to noise ratio. So,if we want to getmore high SNR,we must improve Sampling rate,at the same time we should consider reducethe clock jitter.Clock jitter exist in all aspects of digital audio decoder system. clock jitter accumulationeventually led to the error rate increased, muffled, the sound quality was also affected, it isnecessary in the design of digital signal chain must be on each level to control the time basejitter, in order to eliminate jitter. This officially starting from the data and the time base, whiledata and time-base signals are processed to obtain the best signal to noise ratio. This issue isbased on the audio decoder-jitter, in order to improve the overall performance audio system asa starting point, were studied for the digital audio signal and the clock information processingmethod, Found through research to get better audio digital signal of the input signal isoversampled interpolation filter, the clock signal needs to be better approach is to requirere-use PLL. The subject of the use of eight times over-sampling processing in the FPGA inorder to improve signal to noise ratio, reducing the difficulty of back-end analog filter design, the use of phase-locked loop can provide a more pure time-base signals to improve systemperformance. The issue in the hardware system to accept data segments using CS8412asdigital demodulation, the recovered clock signal and data signal, and then rose through theFPGA to do eight times the frequency interpolation filter, and also the jitter clock signalprocessing, digital audio output access back-end signal to do the PCM1702digital decoding.The subject is the first clock signal and clock data through CS8412total mass of the clocksignal separation and recovery, will separate out the data signal and clock signal into theFPGA; The data in the FPGA8times over-sampling process, the time base signal using asecond-level phase-locked loop for noise reduction, lower jitter, then the access to thePCM1702, PCM1702decoder chip to provide lower clock jitter signal and noise higher thanthe data signal.As digital communication systems, coding and decoding the time base control widelyused in the design of data and time-based signal separation processing for digitalcommunications industry is important.