Design Of Phase Locked Loop For External Synchronous DC-DC Converters

With the development and progress of electronic systems,application requirements increased to promote the Internet,Internet of things and information security system to develop.The chips with different functions are integrated into one system which power requirements are also different.In order to reduce the impact of each other to increase the stability of the system,the system requires power chips can have a stronger compatibility.In this paper,the use of an external synchronous DC-DC converter can be flexible choice of switching frequency to improve the compatibility of the advantages.A charge pump phase-locked loop(PLL)circuit is designed and applied to an external synchronous DC-DC converter.Firstly,this paper introduces the background and significance of the design,and points out the power management chip market situation and development trend.The influence of switching frequency of DC-DC converter on its performance and application environment and the advantages of phase-locked loop DC-DC converter are introduced.At the same time,the structure of PLL and the related parameters are introduced.The dynamic characteristics of two kinds of phase-locked loops are analyzed,and the second structure without static error is adopted in this paper.Then the circuit of charge pump phase locked loop is given respectively.The charge pump circuit is optimized and the reference source is used to ensure the charge and discharge current stability of the charge pump and the reference source also provides bias current and reference threshold voltages for subsequent circuits.The design of a specific voltage-controlled oscillator circuit,the gain can be changed with the external synchronization frequency to reduce the system lock time.And its control voltage is limited to within the specified range so that the clock in the predetermined frequency band range can be locked and the clock which is not within the prescribed range is masked.Finally,based on the TSMC 0.18um CMOS process model,we use Candence software to draw the specific circuit diagram and use Hspice software to simulate each sub-circuit and the whole circuit.The simulation results show that the PLL can synchronize the external clock of 500KHz to 2MHz in the temperature range of-20? to 120? under the power supply of 3V and TT,SS,FF corners.The maximum lock time of 68us minimum 27us,power consumption is less than 223.8uW.And the system can shield the external clock when the control voltage of the voltage controlled oscillator is outside 0.68V to 1.14V.Circuit indicators are to meet expectations and in the DC-DC converter applications have a high practical value.