ASIC Design Of UHF RFID Reader Digital Baseband Compatible With ISO/IEC 18000-6C Standards

IOT(Internet of things) is the significant trend of information network, which is considered as the third wave of the world's information technology following the computer and internet.As the key technology of IOT, Radio Frequency Identification(RFID) technology has become the focus of the market.The research on RFID technology is developing rapidly recently and the RFID reader plays an important role in RFID system. It is responsible for reading and writing the information to tags. UHF(Ultra High Frequency) is widely used in RFID application. The EPC Class-1 Generation 2 (C1G2) protocol is the latest protocol for specialized UHF readers/tags, which was absorbed into ISO standard as ISO/IEC 18000-6C. Both industry and academia are dedicating on the research of single-chip UHF RFID reader system, while there are still few product of single-chip RFID reader in the market now. This dissertation researched on the system structure, FPGA verification and ASIC design of the UHF RFID reader digital baseband which can work well in the SoC system of single-chip UHF RFID reader.The research objectives and achivement of this dissertation are as follows:Firstly,system structure design of the UHF RFID reader digital baseband system based on ISO/IEC 18000-6c standard,in which the transmitter employed PIE encoding at the data rate of 40bps,emited I/Q orthogonal signal for ASK modulation by analog and RF module;The receiver adoped FMO decoding at the data rate of 80bps,recevied the signal feedback which is demodulated by the analog and RF module;Secondly,in order to realize the SoC single-chip UHF RFID reader,this dissertation proposed the struture to implement the communication of the reader and the outside controller by a UART controller, incluing the switch of the state machine,transmitting and receiving commands, which can be applied in different occasions; The signal feedback by the tags can be realtime displayed on the screen of the PC and can be stored.Thirdly, the RF module and Analog of the UHF RFID reader system are integrated by PCB board to a test system with RFID digital baseband,the reader transmited the signal to the tag and received the signal from the tag successfully under the control of the UHF RFID reader digital baseband.Fourthly, based on the RTL coding and FPGA verification of the UHF RFID reader digital baseband, with Design Complier for synthesizing, Primetime for static timing analyzing and Astro/IC compiler for physical design.and GDSII generation finally signed off for tape-out and the die area is 2*2cm2.Fifthly, low power methodology are adopted during the ASIC design and physical implementation such as clock gating which can optimize the power consumption of the digitalbaseband to almost half.The UHF RFID reader digital baseband presented by this dissertation can be used as an IP core in single-chip RFID reader SoC system, which settle a solid technology foundation for the in-depth research of the IOT technology.This dissertation's work is supported by project "Key IP cores design for the embedded multi-mode multi-band transceiver" under the state key item of "core electronic devices, high-end general chips and basic software product" (Project number:2009ZX01034-002-002-001-02).