| In recent years, the networking of things industry known as the third wave of the information industry after computer and the Internet develops rapidly. As an important part of networking of things technology, RFID technology has widespread concern and rapid development. 860-960 MHz UHF RFID technology due to long-range, fast, strong anti-jamming ability etc. has potential applications and broad market prospects in warehouse management, logistics tracking, automatic control and other fields which is the RFID technology research focus currently.To promote and regulate the domestic RFID industry development, China released the " radio frequency identification 800/900 MHz air-interface protocol" in September 2013. Compared with the standard protocol in the field of international, national standard has independent intellectual property rights in coding, definitions and other aspects of instruction.This paper based on national standards for air interface protocol, aimed to design the single-chip RFID reader, on the basis of existing research of UHF RFID reader technology at home and abroad in recent years, put forward the overall structure of the reader system design by research and analysis of RFID reader system, and focus on the digital baseband system design and implementation. Finally the designed UHF RFID reader digital baseband is implemented and verified on FPGA. The main contents and results of this study are as follows:First of all, analyze the details of the newly released super high-frequency air interface protocol standards in our country, including transmit and receive in physical link layer, the tag identification layer, the RFID system commands, the reader and the tag communication process and the anti-collision mechanism. Propose the overall structure of the UHF RFID reader on the basis of national standard protocol analysis, and focus on the digital baseband system, whose function module includes a transmitter link, receive chains, SPI interface and protocol processing unit.Then analysze the principle and design method of some key modules to determine the design parameters. For the design of pulse shaping filter circuit, combine the TPP coding with pulse shaping, accomplishing the two functions together. The designed pulse shaping filter circuit has adjustable order and ran-off, small circuit area and short delay. Because the tag signal have 20% deviation in maximum, in order to reduce the error rate, this paper use edge detection type clock synchronization scheme to achieve symbol synchronization, with advantages of small resources consumption, fast synchronous and good performance.Accomplish the design of the RFID reader digital baseband system of each circuit module including the CRC check, FIFO, coding and raised cosine filter, Hilbert filter, CIC liter sample in transmit link; channel filtering, automatic increase control, clock synchronization and decoding in receiving link; SPI interface circuit and protocol processing unit.The RFID Reader digital baseband circuit designed in this paper is implemented with the Xilinx FPGA Virtex-5 family XC5VLX110 T using ISE completing the circuit synthesis, placement and routing. Complete the digital baseband circuit functional simulation and FPGA verification & testing. |
