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The Research And Application Of Memory Test Algorithm

Posted on:2018-11-03Degree:MasterType:Thesis
Country:ChinaCandidate:Z TangFull Text:PDF
GTID:2348330512996766Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the development of integrated circuit technology,the status of memory in integrated circuit products has become increasingly important.As the capacity of the memory chip becomes larger and the integration is getting higher,the transistors inside the memory and other components become denser and denser,resulting in various physical failures or great increase of the defects probability in the memory chip,especially at low voltages,these conditions are more likely to occur.Therefore,it is particularly important to study a fast test method for detecting memory failures.Aiming to study the algorithm of test memory chip,its verification and application,the thesis conducts into following parts:(1)Depending on the causes and principles of the common faults of the memory,the thesis established a sensitization operation sequence,which again is the basis of the March elements of testing the faults.Integrating the optimization of March test elements,the thesis present new test algorithms.Except for covering common memory failure,with a low complexity,this algorithm improves the memory testing speed by saving about 11.5%of the testing time compared with the March SS algorithm.(2)According to the causes of the memory failures and fault description,a memory failure simulation verification system is designed,which is used to check whether the new test algorithm covers the common faults(stuck at faults,transition faults,coupling faults,address decode faults,disturb faults,stuck open circuit faults,etc.)(3)By designing the memory,the thesis makes a built-in-self-test circuit system to achieve the function of the algorithm,and accomplishes the design of each module circuit and function simulation.The front-end design and back-end layout of the whole circuit are completed by the SMIC 40nm manufacturing process.Finally,the highest frequency of the back-end layout simulation reaches up to 500MHZ while the layout area is 229.9um × 243.6um.This thesis finally designs a new test algorithm-March FM which can quickly detect the common faults of the memory,and it was verified in practical application.
Keywords/Search Tags:Memory, Test Algorithm, Memory Fault, Fault Simulation, BIST
PDF Full Text Request
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