Design And Verification Of An Improved March Algorithm Based On SRAM Built-in Self-test

With the rapid development of Integrated Circuit Design(IC)and the Internet,System-on-Chip(SOC)has become one of the essential aspect of integrated circuit design.The storage capacity and integration of memorizer increased rapidly after the application of very-deep-submicron technology(VSDM)and data storage.However,the number of memorizer transistors increased and the circuit structure design became more complicated which resulting failures and defects of the memorizer more easily.Therefore,memory test has become a key process in chip design,and it is necessary to select a test method with short test time and high fault coverage to complete the memory test.This thesis completes the memory test by Memory-Built-in-Self-Test(MBIST)method,and improves the March C+ algorithm.In addition,a new algorithm,March CS,was proposed to cover the fault that the original algorithm can't detect.The main works are as following:First of all,this thesis analyzes some testability design methods of memory,and selects the Built-in-Self-Test(BIST)method to complete the memory test.It also introduces memory to observe fault conditions at multiple levels of abstraction,as well as major memory fault types.The concept of memory fault primitives is introduced to represent memory static faults and dynamic faults through primitives.Then,the common test algorithm of memory is described,and the March C+ test algorithm is improved.By adding the read and write operations of the original algorithm elements to sensitize the fault of the storage unit,a new algorithm,March CS,is proposed to cover faults that the original algorithm cannot detect.The March CS algorithm can distinguish the read status values of the read failure fault(RDF)and the transition fault(TF)when detecting a memory fault.And the improved March CS algorithm provides more comprehensive coverage of memory static and dynamic faults,improving fault coverage.Finally,the design of the built-in self-test circuit is completed,and the March CS algorithm is customized by the MBIST Architect tool to complete the circuit generation of the test algorithm.The 1024*32-bit SRAM memory generated by the memory compile is simulated.By setting the fault of the SRAM and then sensitizing the various fault states of the memory,the new algorithm is simulated and tverified by ModelSim to detect the coverage.The application of a low-power 1024*32 SRAM chip is tested by FPGA.The coverage of the static and dynamic faults by the March CS algorithm is 91.67% and 76.93% respectively.