Research On Testing And Fault Repair Technology Of Ferroelectric Memory

As a new type of memory,ferroelectric memory(FRAM)has the advantages of high access speed of volatile memory and the advantages of non-volatile memory without data loss when power-off,making it a hot research topic in the memory field.For reducing manufacturing and use costs,improve data reliability,it is particularly important to perform effective testing and repair during the production and use of FRAM.Especially through the online test,the faults of FRAM could be detected and repaired during use,this will greatly improve the service life of the product.Therefore,the main research content of this thesis is how to realize the online testing and self-repair of FRAM better.The main works of this thesis are as follows:(1)Starting from the 2T2 C type ferroelectric memory cell,various physical defects that may occur on single or multiple memory cells are explored.According to the basic read and write timing of the FRAM cell,the access anomalies caused by physical defects are analyzed in detail.(2)The online testing of FRAM is studied,and an online testing method with data backup and recovery functions is proposed.To reduce the area consumption of the data backup module,a block-by-subarray test method is adopted based on the divided block design technology of the memory array.In addition,some test vectors are added to realize the detection of inter-bit coupling faults,which helps to improve fault coverage.(3)In order to optimize the defects of the traditional row-redundancy repair scheme applied in the new memory array structure,a redundancy repair scheme with online selfhealing is proposed.This scheme combines a hardware-oriented redundancy analysis algorithm,a content addressable memory(TCAM)and a small capacity RAM,realized the fault type identification and redundant resource allocation for faulty cells.By subdividing the granularity of redundant resources,the fault repair capability of FRAM is improved.(4)A ferroelectric memory array circuit of a 1Mbit FRAM is designed based on the divided array technology.And a optimal redundant resource architecture is designed for the main memory array,which helps to solve the problem existing in the cluster fault repair of the traditional redundant structure.(5)A redundancy analysis algorithm is proposed to realize the characteristic analysis and address remapping of the faulty cells.Through the analysis of pseudo code,repair example,software modeling,and hardware implementation,the basic principle,execution process,fault repair rate and other aspects of the proposed algorithm are described in detail.The results show that the proposed algorithm has nearly 90% fault repair rate when dealing with a large number of cluster faults.Finally,Verilog HDL modeling and schematic diagram description are used to realize the core circuit module of the proposed redundancy repair scheme.