The Research And Design Of A 2-bit/cycle High-Speed Energy-Efficient SAR ADC

In recent years,with the development of wireless communication systems and Ethernet,the demand for high speed,medium resolution and low power consumption ADC(Analog-to-Digital Converter)is increasing.Although the speed of Flash ADC is very fast,its hardware consumption increases exponentially with the increase of resolution,so it is suitable for the case of low resolution.Although ADCs of other structures can achieve lower power consumption and smaller area than Flash ADC,but it is still difficult to meet the requirements of modern communication systems for low power consumption.The power consumption of SAR ADC is very low,but it needs N conversion cycles to achieve N bit resolution,which limits its speed.Single channel sampling rates of SAR ADCs on the market can hardly reach 100 M.With the development of modern technology,the constant reduction of device size and the continuous improvement of device speed make the high-speed SAR ADC possible.High speed SAR ADC has become a research hotspot nowadays,many top teams at home and abroad have studied it,and have made some achievements.Many new types of structures and techniques have been proposed,such as asynchronous clock,redundant CDAC,multi-bit/cycle,time interleaved SAR ADC,alternate comparators,etc.This project adopts a 2-bit/cycle SAR ADC structure,which almost doubles the conversion rate of SAR ADC,because it can finish the conversion of a 2-bit digital code for each conversion cycle.This design uses a segmented CDAC to reduce the number of capacitors,thereby further reducing the area and power consumption.The use of split cap reduces the layout area of common mode voltage.The bootstrapped technique not only improves the linearity of the switch and decreases the harmonic distortion of the ADC,but also eliminates the charge injection effect and improves the sampling speed.In this paper,the traditional double-tail comparator is discarded and replaced by modified double-tail comparator.Compared with the traditional double-tail comparator,the requirement of the modified double-tail comparator for timing is enormously reduced.The new structure can not only achieve high speed,but also cut down the noise and mismatch.The self-calibration technique is simple in structure and low in power consumption,because it doesn't require a quiescent DC current.The use ofasynchronous logic reduces the time redundancy and improves the time utilization ratio,so that ADC can achieve higher conversion speed.The common-centroid layout reduces the system mismatch.This subject is based on the SMIC 55 nm technology and 1.2V power supply to complete the design and simulation of a fully differential 2-bit/cycle SAR ADC,the common mode voltage is 0.9V,the differential input voltage range is-400mV~400mV.At the sampling frequency of 500 MHz and input frequency of 220.7MHz,ENOB can reach 7.81 in the tt corner.Power consumption of the digital part is 4.97 mW,power consumption of the analog part is 3.8mW.Total power consumption is less than 9mW,which meets the requirement of low power consumption.