Research And Design Of 14-bit 250MS/s Low Power Consumption SHA-Less Pipelined ADC

As IC fabrication technology continuously progress,semiconductor foundries can provide faster devices,which greatly promote the development of digital circuits.Therefore,digital signal processing(DSP)method has been wildly adopted.How to convert analog signals to digital signals is of great importance.ADC(analog to digital converter)is a kind of device converting analog signals to digital signals.It is always described as a bridge that connects the analog world to digital world.Pipelined ADCs have been regarded as one of the most important choices in wireless communication systems.How to realize high speed,high resolution as well as low power consumption at the same time has become the research hotspot.The operation principle and the non-ideal effect are introduced in detail in this thesis,with taking the first pipeline stage as an example.The first pipeline stage consists of a sub-ADC,sub-DAC(digital to analog converter)and MDAC(multiplying DAC).There are two sampling network in the first pipeline stage,namely,sub-ADC and MDAC.If there are any mismatch in the bandwidth or sampling instant,it would have a great effect on the performance of the total ADC,especially at high frequency.The mismatch of capacitor array in the sub-DAC will have a great impact on INL,leading to a relatively low SFDR.Moreover,The finite gain and settling time of the residue amplifiers are the other factors which may cause linear error or non-linear error.Besides,the residue amplifiers contribute most of the power consumption of the total ADC.A high speed,low power consumption 14 bit 250MSps SHA-Less pipelined ADC is presented in this thesis based on SMIC0.18 um 1.8V 1P6 M standard CMOS technology.The chip has an area of 3355?m×3355?m.To achieve high speed and high resolution,a configurable bandwidth method is adopted to achieve bandwidth match.As for the DAC capacitor array mismatches and errors in the residue amplifiers,a foreground calibration algorithm is introduced,which is proved to be useful in promoting the performance of the ADC.To achieve low power consumption,this thesis adopts a novel complementary switched capacitor amplifier and a cascode compensation technique.In addition,the input common mode voltage can be set relatively low,which will reduce the power consumption of the clock driven circuits.The input range of the ADC is 2Vpp.When applying a input signal with a-1d BFs amplitude,the simulation results show that the resolution can be still over 10 bit even ata frequency of the input signal over 300 MHz.The total power consumption is 250 m W.