Applied To Wlan Receiver Of Continuous Time Sigma Delta Research And Design Of The Modulator

With the ever improvement of wireless communication technique in recent years, data converter featuring wideband and low power has been enjoying great popularity as a research hotspot in both academia and industry. Thanks to its unique techniques of oversampling and noise shaping, sigma delta ADC effectively filters out inband noise and enhance signal-to-noise ratio. Continuous-time modulator (CTSDM) has gained overwhelming advantage over its discrete-time counterpart, in addition to design complexity of prefilter in the receiver system.Aiming at the wideband requirement from wireless communication, this dissertation studies and designs a sigma delta modulator with10MHz signal bandwidth and12bit resolution. The modulator implements the active loop filter with a proposed feedforward-feedback (FF-FB) mixed architecture and adopts4-bit quantization and4-bit current feedback, improving the performance of the modulator and ensuring stablility of the loop.The design involves:synthesizing the respecitive gain coefficients of the loop filter which satisfies the required Noise Transfer Function; system buidling with simulink simulation platform and modeling the influence of various nonidealities on the overall system, such as DC gain and finite gain-bandwidth product, offset and excess loop delay of the comparator, mismatch from feedback D AC as well as clock jitter; in succession, Verilog-A modeling in spectre environment, thus specifying more detailed circuit parameters; finally, the implementation of circuit blocks, including design and optimization of opamps, comparators, latches, DACs and clock generators, etc.The modulator is realized by SMIC0.18um CMOS Mixed Signal process. Operating at the clock frequency of320MHz, the core consumes27.3mW power dissipation and reaches84.75dB SNDR under1.8V power supply.