Modeling And Design Of Ring Oscillator Based Continuous-time Sigma-Delta Analog To Digital Converter

The decrease of CMOS feature size and power supply makes those ADC, which using voltage domain quantization, have no longer advantages in quantizer’s accuarcy. In contrast, those ADC using time domain quantization takes advantages of high time domain resolution for the process’ s update. This thesis proposes a Double RVCO Quantizers(DRQ) based Continuous-Time(CT) Sigma-Delta(ΣΔ) ADC architecture combining the RVCO Quantizer with the lower power ΣΔ architecture, for the low power requirement of today’s intelligent portable electronic products. The CT ΣΔ ADC was designed in GSMC0.18 process with 10 MHz bandwidth and 10 bit accuracy and was suitable for WLAN protocol application. The thesis’ s specific contents as follows:Firstly, it studied the principal of the ΣΔ modulator, as well as the merits and drawbacks of the CT and Discrete Time(DT) architecture. Meanwhile, it also presented the property of the ring oscillator and its application in CT ΣΔ ADC. Based on the conclusion and the analysis of previous ADCs which based on RVCO Quantizers, it presented a DRQ based CT ΣΔ ADC architecture.Using the CPPSIM software to model and simulate the system, it presented the RVCO Quantizer, NRZ DAC and the third order filter’s CPPSIM modeling and simulation. The analysis and modeling of the system’s non ideal factors, such as the finite operational amplifier’s gain bandwidth product, resistor noise, NRZ DAC noise, clock jitter, are also presented. The system’s behavioral simulation confirmed the design parameters’ range and achieves 67.9d B/65.4d B/72.5d B SNR/SNDR/SFDR.It presented the transistor level’s circuit design of the RVCO Quantizer, NRZ DAC and third order filter in GSMC0.18 process, also showed the optimal filter parameter and analysed the filter’s input noise and its RC parameter tuning. The system’s transistor level simulation showed SNR/SNDR/SFDR 61.5d B/55.0d B/56.5d B, which met the design aim. The spectrum analysis of the output signal showed that the proposed architecture can restrain the even-order harmonic and increase the system’s SNDR effectively.The thesis drawed conclusions for the study in the end. It pointed out the creative points and limits as well as some research trend of the RVCO Quantizer based ADC.