The Research On FPGA-based Soft Error Sensitivity Estimation Method For Microcontroller Core

Along with the continuous developments of semiconductor technology,the chip integration, operating frequency, power consumption and other indicators are increasing.However, the reduction in the feature size also reduces the critical charge required to flip the circuit, making microcontrollers more sensitive to both internal and external environments. On the other hand, the microcontrollers have been widely applied to some special application fields which request high reliability, such as aerospace. In the space environment, the microcontrollers are vulnerable to single particle effect. When an energetic particle strike occurs on a logical unit in the microcontrollers, the logic value of the unit will be flipped, which seriously affecting the reliability of microcontrollers. Fault injection is a flexible, convenient, cheap and effective method, which is widely used in the field of reliability evaluation. In the implementation of fault injection, commonly used methods are physical fault injection, simulation fault injection and FPGA fault injection.In order to automatically and quickly analyze the soft error sensitivity for microcontroller,this dissertation studied the FPGA-based soft error sensitivity estimation method for microcontroller core.Firstly, the research status of the FPGA-based fault injection method of microcontroller,the internal structure of FPGA, the development environment and language are simply introduced. Secondly, PIC16F54 microprocessor components are designed by using Verilog HDL, including fetch instruction, decoding, ALU, register set, stack, and ROM.Then, the design is verified on FPGA development board. Thirdly, the microprocessor ischosen as the experimental object, a soft error sensitivity analysis method using FPGA-based fault injection is proposed. The fault and fault-free microcontroller on a FPGA board run simultaneously. Moreover,a fault injection controller, a fault classification module and a fault list module are also implemented on the hardware. The method inherits the parallelism of the FPGA and achieves a fast and automatical fault injection for all storage bits. Lastly, approximate 300,000 soft errors are injected, and the sensitivity results are compared with other methods to verify the correctness of the proposed method.Compared to the simulation fault injection, experimental results show that the proposed method achieves four orders of magnitude speedup.