Design Of A Fast Fault Injection Platform For Modeling Single Event Upset On Virtex-6 FPGA

The space environment contains a large number of high-energy particles.The SRAM-based FPGA working on the spacecraft will be radiated by these high-energy particles,causing the circuit to undergo single-event flipping,leading to circuit functional errors on the FPGA.As the size of the semiconductor manufacturing process increases The smaller the FPGA's power supply voltage and the lower the internal node capacitance,the more serious the single event flip.In order to evaluate the sensitivity of the user circuit on the FPGA to single event flipping,this paper uses the Virtex-6 FPGA development board to build a single event flip fault injection platform,and simulates the single particle flipping fault on the Virtex-6FPGA to realize the user circuit pair Assessment of particle flip sensitivity.First of all,this paper analyzes the basic structure of Virtex-6 FPGA and the mechanism of single event flipping inside the FPGA,and determines the single event flip fault injection model: by flipping the frame data bits in the Virtex-6 FPGA configuration memory to simulate single event flipping Fault;then,read back the configuration register of the Virtex-6 FPGA through the ICAP interface,flip the frame data bit read back and write it back,so as to inject the single event flip fault into the user circuit on the Virtex-6 FPGA;build a Virtex-6 FPGA single event upset fault injection platform,which realizes continuous and multiple injection of single event upset faults into Virtex-6 FPGA user circuits,and then accurately evaluates the sensitivity of user circuits to single event upset when running on Virtex-6 FPGA;in order to improve The efficiency of fault injection,the rapid fault injection technology is researched,and the fault repair in this f ault injection and the frame data readback in the next fault injection are executed in parallel through the parallel processing method,so as to optimize the fault injection process and improve the efficiency of fault injection;In order to facilitate the use of the Virtex-6 FPGA fault injection platform,with the help of Perl scripts,GTK2-Perl toolkit and ISE commands,the graphical user interface of the fault injection hardware platform is developed,and the circuit to be evaluated is automatically mount ed to the fault injection platform,as well as implementation and fault injection.Relevant modules and parameters are configured,and the steps of synthesis,translation,mapping,placement and routing,and timing check are carried out in sequence,and fi nally a bitstream file for SEU fault injection into the hardware platform is generated.