Design And Implementation Of High Speed Remote Sensing Satellite Image Data Transceiver System Based On FPGA

Remote sensing satellite system has been extensively investigated owing to its widely application in military area as well as in daily life. It is great significant to develop ground satellite receiver and matching satellite simulator for inconvenience in developing receiver alone. Here the research statue and trends of satellite image transceiver system were broadly investigated and summarized. The scheme was then proposed for the system architecture of simulator and receiver.The system architecture based on FPGA was established via analyzing design goals and technical requirements. The hardware system was composed of FPGA and peripherals on Xilinx ML605 to realize data transfer and processing. PCIE DMA high-speed interface was designed to transmit data between ML605 and PC. The problem of multiple modules to access single DDR3 SDRAM simultaneously was solved by adopting DDR3 multi-port memory controller based on AXI4 bus. Destriping and channel coding/decoding module interface were designed, integrating functions of image processing and CCSDS channel data processing. The software system involved application and driver. Here application was designed to interact with user, associating with driver to control image transceiving.Both the hardware and software modules were tested and verified. Hardware test was based on FPGA resource usage and timing, performance of DDR3 multi-port memory controller(MPMC) and destriping interface, while software test aimed at verifying the application function and DMA transfer bandwidth. Result showed that modules in satellite transceiver system met design requirements including image transceiving, data storage, channel coding and decoding, destriping and image displaying module. Performances of some modules remained underdeveloped, but the system here laid a foundation for further research on satellite image transceiver system.