Low Power Design And Verification Of A SoC Chip With Two Core

With the development of the microprocessor performance,power consumption has become a very serious problem,even a major obstacle of the processor development.Most of the traditional technology of low power consumption were used to reducing the dynamic power consumption.Recently with process entering deep submicron level,the proportion of static power consumption increases,even has exceeded dynamic power consumption.Therefore,dynamic and static power consumption all need to be optimized in integrated circuits design.This paper proposed a full low power design solution of the LPE processor,which is a new designed dual-core SoC.Several low power technologies were used in this processor,including clock-gating,power-gating and DFS.A power management controller(PMC) has been designed to efficiently schedule these methods so that effectively reduce both the dynamic power and static power.PMC was implemented in this project.Several new registers were defined to describe the function of Power Configuration,Power States,Power Down Intervals and Power Down Tag. For each core and IO controller,DMAC,PEU and GMU,a FSM was designed to control the flow of standby,wakeup, power down and power up,leading the processor into different low power mode by dynamic or static power reduction.In the paper,a UVM based unit level verification platform was built for PMC.With this platform, the paper has verified the access path of registers,the state transition of the function of standby,wakeup,power down and power up.In addition,a system level low power verification platform of LPE was set up to run a CPF-based low power simulation.With this platform,this paper has verified the control function of each power domain in LPE,the isolation cell usage and the normal function in each power mode.In the end of this paper,PowerArtist was used to analysis and evaluate the power of LPE processor in RTL level.Results show that,the solution this paper proposed can effectively reduce the dynamic and static power of LPE processor.