The Hierachical Physical Design Based On QX Multi-core Chip

With the development of technologies and manufacturing process in the integrated circuit (IC) design, along with the increasing demand of market, how to complete a complex layout design in time is that more and more designers have to face. On the other hand, in the dual role of requirement guiding and technology driving, the idea of integrating the system on a chip comes forth, named the system-on-chip (SoC). Now, integrated circuit is in the time of SoC.In the SoC design, physical design is an important and difficult problem. Because of the process size shrinking, many new problems will appear, the design is becoming more complex, such as crosstalk, voltage drop, the antenna effect problems, and even the design for manufacture and design for yield also need to be considered in physical design. Physical design is the bridge between the top system planning and low-level model, so it will occupy a very important position in the whole flow integrated circuit design.In the QX Multi-core SoC Chip design, we have studied a series of problems about the physical design. According to the chip-scale, structural features and complexity of the chip, we have used a hierarchical physical design method which combines Top-down and Bottom-up phase, and have gotten a good result. In this paper, the main research work description is as follows.Analysis general situation of the current SoC design and the design of multi-core processor.Explain the reason that we have used the hierarchical physical design.Analysis the two main issues-timing closure and signal integrity problems in the design process in detail.Resolve the problems in the physical verification process, so enhance the reliability of the system.In the typical condition, the clock frequency comes to 350 MHz, and meet the system design aim.