Hierarchical Physical Design Of The Core Pac In YHFT-X DSP

With the constant development of the IC design and the expansion of the chip scale, the convergence of the timing becomes more and more difficult and the iteration period gets longer and longer. Therefore the back-end realization nowadays encounters grave challenges. This paper, applying the physical realization of YHFT-X DSP as an example,dedicates to solve the timing convergence issue via hierarchical physical design approach.YHFT-X is a highly efficient DSP chip manufactured under 40 nm process and works at a frequency as high as 1GHz in worst case. Its design now is still under evaluation stage. This paper arranges the chip’s core structure in a hierarchical way and regarding the intense timing logic module as well as the large area second-order data cache module, it executes hierarchical design to acquire convergence. Finally by iterating the hierarchical design back to the top layer and optimizing the top level physical design it can realize the 1GHz requirement.The paper’s major tasks are as follows:1) The Logic Operation Module Optimization and Consolidation Based on Micro-architecture.As for the intense timing logic of the arithmetic unit, especially for the fixed logic operation module with single clock instructions, it adopts micro-architecture optimization method to elevate the timing by 16.4% and reduce the area by 15.5% at the same time. In the physical design level, the logic operation module acquire timing convergence via efficient placement and routing. Then after equivalent verification and physical verification,extract timing library(.lib) and process library(.lef).2) The Level Two Cache Memory Physical Design Based on Hands on Custom.As for the level two data cache which occupies 50% the area of the entire core, implement topological structure plus hands on design to the control circuit and then divide this cache into segments when operating physical design. Regarding the internal logic of every sub-module, insert buffer, control register and read/write unit to achieve the reasonable dispatch. When finish the sub-module design, execute top layer assembly by resource multiple access. In the top layer layout design, properly place the wire routine and reserve track to control the wire length. In the clock network design, use hands on design in the main clock and it reduces time delay by 9.4% and time offset by 22.9%. Finally hands on designmethodmakes the physical design 75 ps less than that of automatic design.3) The Hierarchical Physical Design of the Core.As for the CorePac hierarchical design, according to the data flow relation and the macro blocks’ placement, rearrange all the sub-modules’ location and in the power/ground design, insert decoupled unit and control the standard cell’s density to restrict the IR-Drop of the whole CorePac within 5%. In the clock network design, adopt doubled wire width and doubled wire clearance to mitigate clock deviation and time delay. In the global interconnection design, insert repeaters and properly configure the wiring channel to reduce the crosstalk effect. At last apply low threshold unit to modify the illegal path so that it can facilitate the 1GHz goal and verify the feasibility of this project.