SoC Low Power Design-Clock Management Design Of Beam Steering SoC

Along with the development of the integrated circuit manufacturing process, Chipintegration more and more high, in recent years, the prosperous development of the SystemChip SoC (System on Chip, System integration Chip) can will more functional integration inthe same Chip, however Chip power consumption also become more and more big, powerconsumption has become the bottleneck of Chip design. At present, the low power designinggradually become an important research direction in the design of SoC.This paper mainly around SoC low power consumption on research and design, anddesigned a kind of low power management strategy to dynamic configuration SoC chip clockfrequency. The paper first introduces research background of low power area, summarizes thedevelopment and status of low power research work; and then analyzes both dynamic andstatic power of CMOS circuits．According to the model of dynamic power consumption, thechapter summarizes the system level, system structure level, the register transmission grade,gate level and circuit level low power consumption design method, finally put the emphasison the research and analysis gate-clock technology, uses EDA tools for its realization.Then, a dynamic power management controller (PMC) is adopted which dynamicallychanges the work modes and clock frequency according to applications, improves its clockchoose circuit design, designs clock source switching circuit without burr, which can verygood to eliminate the burr. In software control, we define the conditions of system powerstates transition and the transition process between states. We also give a detailed elaborationof dynamic management scheme of modules inside the processor.Finally, using Power Complier software, through the gate power consumption level wesimulate different working conditions of the chip. In NORMAL mode of60MHz working frequency,power consumption for372.5mW; in the SLOW mode of5MHz working frequency, power consumptionfor62.3mW; in SLEEP mode, power consumption is only0.124mW. The results show that the lowpower consumption management strategies of the dynamic configuration SoC chip clockfrequency have been achieved good results, effectively reducing the power consumption ofthe chip.