Design For Testability Of YHFT-XX Chip Test Low Power Design And Optimization

As integrated circuit design size increasing, the complexity of the improved and the shorten of design cycles, chip testing faces many problems to be solved, becoming the bottleneck of the development of integrated circuits,.Therefore, design for testability(Design for testability, DFT) paly an increasingly important role in design of chip. To be the perfect test, we need to consider many testabily requirements. Such as the area overhead, test power, demand extra pins, and select the appropriate testing strategy is even more important. The various DFT strategies are rationally applicated. From the test perspective,it can improve chip testability?improve fault coverage?reduce test hardware overhead and power consumption; From a functional design perspective, it can affect the function of the test to a minimum. In this paper, according to the require that DFT of YHFT-XX chips, making analysis and structural optimization to method of testability technology, using the top-level scheduling controller implement low power test,meeting the test quality requirements and reduce test costs while ensuring quality and time to market chips. The main work is as follows:1. Analysising YHFT-XX chips face with the problem in terms of design for testability, based on low power block test put forward the solutions. In order to reduce the power consumption of combinational logic scan test, on the part of the enhanced scan logic insertion barrier gate improve. The problem that the internal module block test port can't direct accessed, putting forward two test access programs that wrapper sharing and bypass logic that showed good effect in the YHFT-XX chips. Wrapper Shared structural area can be reduced by 61.79% and the bypass structure can be reduced by 87.60% compared with the traditional structure of Wrapper,.2. Optimizing the bypass logic of Memory Build-In Self Test(MBIST), savings the bypass area overhead, reducing the number of logic which timing unit. The scan test power is slightly reduced,. Especially, a design contains a large number of memory, this optimization can reduce hardware overhead, it can be performed according to the specific circuit structure and test coverage requirements, using the experiment FFT_Ram_inst memory in this paper, in three level exclusive-or gater, the area save50.68%, the scan test power reduce 1.53% in the FFT_top module.3. Using test scheduling controller on the top chips to implement low power test,and the technology can implement scan test and MBIST test unified management. It can be flexibly controlled test start and test results back, the test results back in place where design a MBIST controller output observation chain, To locate the fault of memory when executing ATE test. By testing strategy for pattern chain configuration, controller not only can reduce test pin, but also can reduce test power.The optimization technology and low power test control has been applied toYHFT-XX in text of papers presented, and the test results showed good. Thesis research on the electronic design automation tools also have some reference value.