Research And Design Of A Novel Testing System For Single-Event Multiple Transient In 65nm Process

With the persistent rising of China's overall national strength, the radiation hardened chip is requested urgently for aerospace and military applications. The research about radiation hardened integrated circuits and radiation effect has been becoming a hot topic, so than more and more specialists apply themselves to it. With the rapid development of the CMOS integrated circuits(ICs), the features of radiation effect of the semiconductor devices have also changed profoundly, especially in the Single-Event Transient(SET) features. To the manometer technologies, SET are becoming the main factor for system soft errors and has been becoming the focus of anti-radiation hardened techniques of radiation hardened integrated circuits.In nanometer CMOS ICs, the device has smaller size, and the space between them is reduced, so that the integration density increases. In this case, the multiple node charge collection becomes a pervalent phenomenon with heavy ion striking at semiconductor devices. Due to multiple node charge collection, Single-Event Multiple Transient(SEMT) and Single-Event Transient Quenching(SET Quenching) are observerd in advanced CMOS technologies, especially in ? 65 nm process. These effects increase the complexity of soft error evaluation greatly, such that the research about SEMT is highly required and valuable. Based on these concerns, the technology of the experimental test about SEMT is studied in this paper. A SEMT chip was designed in 65 nm technologies, and heavy-ion experiments were conducted. The experiment result indicates that it is a significant breakthrough in experimental characterization of SEMT. The main works and contribution of this dissertation are as follow:? A novel test circuit was proposed for test SEMT, it has be designed based on one SET test system. The test system ensures survey precise of SET test and synchronous capture of Multiple SETs is the highly precise self-capture circuit. This SEMT test circuit is strict with timing control, and has been designed to hardening.? A novel hit-cell was designed. The previours studies about SET adopted inverters-chain generally which has been used as circuit under test. On the basis of different research purposes, corresponding improvement has been done. The P-hit and N-hit cell was designed to characte the SET generated from PMOS and NMOS, and P-hit and N-hit cell to study effect of the source-extension effect in the process of multiple node charge collection was also desgined.? A novel structure of circuit under test was proposed for test SEMT. Based upon past research experience, a multiple short chain SEMT structure of circuit under test has been designed to vertical interlaced placement. The test results showed that the proposed well structure has good rationality for SEMT mechanism and high accuracy for SET measurement.? The SEMT chip has been designed in 65 nm bulk CMOS process and successful tap-out, and the test system of ground-based testing was also designed to SEMT test. The experimental test system has been designed for SEMT chip test.The experimental results indicate thatthe SEMT test system has implemented all experimental Characterization about SEMT. It has been a significant breakthrough in experimental characterization of SEMT. The methods of SEMT test has provide effective research methods and scientifically experimental data for further research on Single-Event Transient.