Research Of New SOI High Voltage Devices Based On The Technology Of Lateral Variable Reduced Surface Field

LDMOS(Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) is the lateral power device, which has been widely used in power integrated circuits because of its advantages of high voltage, large gain, low distortion. Power integrated circuits with features of high voltage and high current often requires LDMOS devices to have high breakdown voltage(BV) and low specific on-resistance(Ron,sp). BV and Ron,sp are contradictory, and BV is enhanced often accompanied by Ron,sp increasing. Since LDMOS has been proposed, relevant experts have been proposed many theories and techniques to solve this problem, such as junction termination techniques, super-junction technique, enhanced dielectric layer field theory and reduced surface field technology.Based on the lateral variable reduced surface field(RESURF) technology, two kinds of silicon on insulator(SOI) LDMOS structures are researched and analyzed in this paper.One structure is a novel SOI LDMOS with a partial compound buried layer(P-CBL). The buried oxide layer at the source-side is replaced by a compound buried layer of “top oxide-middle polysilicon-bottom oxide”, and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS. Due to the thickness of the buried oxide layer is different from source to drain, the concentration of the interface charges between the top silicon layer and buried oxide layer when the device is at breakdown will meet different lateral RESURF effect. This results in the interface net charges of source-side is higher than the drain-side. A new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV. Impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide at the source-side is thinner than the conventional buried oxide layer, leading to a lower Ron,sp at the on-state and an enhanced vertical BV at the off-state. Thermal conductivity of polysilicon is higher than that of SiO2, offering a lower self-heating effect. The influences of structure parameters on the device performances are investigated with device simulation software MEDICI. Compared with the conventional SOI LDMOS on the same top silicon layer of 4?m, buried dielectric layer of 4?m, and drift region of 40?m, BV of P-CBL SOI LDMOS is improved by 33.4%, Ron,sp is reduced by 37.4% and the maximum temperature at the power of 1mW/?m is depressed by 13.3K respectively.Another structure is a novel SOI LDMOS with a lateral variable interface doping(LVID) profile on the top interface of the buried oxide layer. The LVID layer of the same impurity is placed at the interface between the top silicon layer and the buried oxide layer, the concentration of which linearly increases from source to drain. The drift region is divided into two layers at the vertical direction--uniform doping layer and LVID layer. When the device is at the off-state, the ionized donors or acceptors distributions of the drift region are not uniform as the conventional structure but the combination of uniform doping profile and LVID profile. The LVID layer results in a lateral variable RESURF effect. The concentration of interface ionized charges linearly increasing from source to drain modulates the lateral electric field, and improves the vertical electric field of the buried oxide layer, which results in a higher BV. The influences of structure parameters on the device performances are investigated with device simulation software MEDICI. Compared with the device structures of completely uniform doping and completely lateral variable doping in drift region on the same top silicon layer of 2?m, buried dielectric layer of 1?m, and drift region of 10?m, BV of LVID SOI LDMOS is improved by 34.3% and 23.3% respectively, and FOM(Figure Of Merit) which balances the trade-off between BV and Ron,sp is improved by 43.6% and 36.4% respectively.