Research On Optimization Theory Of The Vertical Doping Profile For Lateral Integrated High Voltage Device

LDMOS (Lateral Double-diffusion MOS) transistors, as the typical representation of lateralhigh voltage devices, are widely used in various PIC (Power Integrated Circuits) because of theirsuperior performance, low price, and easy integration. The contradiction between breakdownvoltage and on-resistance is the key problem of LDMOS. To optimize this contradiction, devicedesigners at home and abroad have done a lot of improvements on the device structure and theprocess technology, LDMOS is in a transition from the homo-doped single RESURF (S-RESURF)structure to the oppsitely-doped double RESURF (D-RESURF), triple RESURF (T-RESURF) anddual conduction layer (Dual-CL) structures. However, for the homo-doped drift structures, theexisting analytical models are mostly based on the approximation of the uniform-doped drift region,without considering the variety of the drift vertical doping profile. For the oppsitely-doped driftstructures, the complexity of the drift depletion makes the theoretical research progress slow.Therefore, it is very necessary to establish a unified theory to help the analysis of the effect of thevertical doping profile on device performance and guide the optimization design of lateral highvoltage devices.In this thesis, addressed the drift vertical doping profile of bulk-silicon and SOI lateral highvoltage device, the theoretical model, the physical mechanism and the full CMOS processrealization are researched. A unified breakdown model of bulk-silicon/SOI lateral high voltagedevice with arbitrary vertical doping profile is proposed for the completely-depleted andpartially-depleted cases. Breakdown models of T-RESURF devices with uniform, linear P-buriedlayers and dual conduction layers are consummated. A new figure of merit (FOM) which takes theimpact of the vertical doping profile into consideration is derived to provide a basic guideline foroptimization. Under the guidance of the above theories, two lateral high voltage devices, the N-wellLDMOS and the P-top layer N-well LDMOS, are developed completely based on the CMOSprocess, and some experimental results are obtained.First, a unifiled breakdown model of bulk-silicon/SOI lateral high voltage device with arbitratyvertical doping profile is proposed. By solving the2D Poisson equation with three methods: thediscrete method, the continuous method, and the equivalent substrate voltage method, analyticalmodels of the2D electric field and potential distributions of bulk-silicon/SOI devices with arbitrary vertical doping profiles are given. The breakdown voltages are formulized to quantify thebreakdown characteristic in completely-depleted and partially-depleted cases. A new RESURFcriterion which can be used in various drift doping profiles is further derived. Based on thesemodels and the numerical simulation, the electric field modulation mechanism and the breakdowncharacteristics of homo-doped drift devices are investigated in detail for the uniform, Gaussian,linear, and two-order doping profiles along the vertical direction in the drift region. Then, thementioned vertical doping profiles of these devices with the same geometric parameters areoptimized, and the results show that the optimal breakdown voltages and the effective drift dopingconcentrations of these devices are identical. The numerical and experimental results have beenshown to support the analytical results for both the completely-depleted and the partially-depletedcases.Second, breakdown models of oppsitely-doped drift devices are consummated. By partitioningthe drift region and using the concept of effective concentration, the potential and electric fielddistributions of the bulk-silicon T-RESURF devices with uniform, linear P-buried layers and theSOI RESURF devices with dual conduction layers are proposed. The electric field reductionmechanism and breakdown characteristics in these devices are discussed. A RESURF dopingoptimal region (DOR) for optimizing the drift region concentration and a theoretical optimumP-buried doping profile are given. The lateral and vertical breakdown voltages of Dual-CL SOIdevices are derived in the form of a matrix equation, considering the influences of the N-top layer,P-buried layer, and the N-drift region. A unified RESURF criterion of S-RESURF, T-RESURF, andDual-CL devices is further derived. These models form an integrated breakdown theory of lateralhigh voltage devices with single, double, and triple drift layer, affording an effective way toimprove the performance of oppsitely-doped drift devices. The analytical model is verified bynumerical simulations and published experimental data.Third, a new theory, which is important for device optimization, is proposed to account forvarious vertical doping profiles. Based on the breakdown model mentioned above, the maximumbreakdown voltage of lateral high voltage device with arbitrary vertical doping profile is derived.The on-resistance is obtained based on the drift region resistance approximation. A new FOMconsidering the arbitrary vertical doping profile is further derived to provide a device optimizationguideline. The obtained theoretical results are further compared against simulation and experimentalresults from devices with various vertical doping profiles on both SOI and bulk-silicon substrates, all showing good agreement. The theory reasonably predicts the performance irrelevant to thedetailed doping profile and only determined by the total doping dose in the device with homo-dopeddrift region. For T-RESURF LDMOS with oppositely-doped buried layer, the theory captures itssuperior performance over other devices.Fourth, two lateral high voltage devices are developed completely based on the0.18μm CMOSprocess. Under the guidance of the above theories and with the deep analysis on the standard deepsubmicron CMOS process, two lateral high voltage devices, N-well LDMOS and P-top layerN-well LDMOS, are developed without changing the process conditions and the process sequence.The process and device simulation by using Silvaco TCAD proves the feasibility of thedevelopment of these two devices. The layouts for the N-well LDMOS and P-top layer N-wellLDMOS are designed and the main design rules are explained. At last, the devices are taped outbased on the SMIC0.18μm CMOS process, and the test results basiclly meet all the primarysimulation results.