Double Dielectric Buried Layer Soi High Voltage Device Development

SOI HVIC(Silicon On Insulator High Voltage Integrated Circuit) is the mainstream and trend of the Power Integrated Circuit (PIC) due to the improved isolation, reduced leakage current, high speed performance, low power dissipation, and perfect irradiation hardness. SOI lateral high voltage devices are the key devices in SOI HVIC. Its low vertical breakdown voltage limits the application in high voltage and power integrated circuit. A lot of novel structures have been proposed to enhance the vertical breakdown voltage of SOI lateral high voltage device. However, up to now, silicon dioxide is used as the buried layer and the breakdown voltage of the applied SOI devices is less than 600V.In this thesis, addressed the breakdown voltage problem of SOI lateral high voltage device,a new structure of SOI high voltage device with the double buried oxide layer is proposed,of which the buried layer is made of two oxide layers and polysilicon between them, with a window on the first oxide layer. The electric field of the second oxide layer is enhanced due to the charges in polysilicon, thereby resulting in enhancement of the breakdown voltage. The window on the first oxide layer and thin second oxide layer reduce the self-heating efficiently in evidence. The technique of Field Plate and low electric field layer is used to improve the lateral breakdown voltage.The breakdown mechanism of SOI LDMOS with the double buried oxide layer, its breakdown voltage is shared by two buried layers, and charge Qs was located near the interface of polysilicon. With more charge, the field of buried oxide was improved basis on entirely continuity of electric displacement vector, and then the vertical breakdown voltage was raised.The distributions of interface charge on the interface of polysilicon, electric field in top silicon and insulation layer were studied for the novel structure by the vertical blocking mechanism. The influences of window's location and width and insulation layer thickness on breakdown voltage were analyzed and compared with analytical results. The dependences of breakdown voltage on the structure parameters are investtigated by MEDICI, and the process is optimized by TSUPREM4. The simulation results show that the breakdown voltage of the new structure increases from 597V of the conventional with the 2.5μm-thickness buried oxide layer to 799V with 2μm and 0.5μm of the first and second oxide layer and 20um-thickness drift region.The fabrication process of SOI material with non-planar buried layer is developed based on SDB (Silicon Direct Bonding) technology. A feasible way to produce SOI material with double buried oxide layer was presented. The process programs of SOI LDMOS were finally given 761V SOI device with the composite buried layer are obtained for the first time. The electric field in the buried oxide layer increases from below 120V/μm of the conventional SOI to over 400V/μm for the second buried layer of SOI device with the double buried oxide layer.