DDR3 Signal Design Method In Optical Network

DDR3 is the third generation of double data rate synchronous dynamic random access memory, which belongs to the SDRAM series.It is the next generation of DDR2. This memory is also the most widely used memory at the present stage.To achieve the purpose of signal integrity and stability status in the system for DDR3, this thesis accomplished research and analysis for DDR3 protocol、interface design、IBIS models、the basic problem for signal integrity deeply. And also, taking into account of program needs, this thesis also performed pre-simulation for DDR3, coworked with other guys to complete hardware schematic design and PCB layout according to the pre simulation result.Innovative works are showed below:Having Studied the DDR3’s topology.According to simulation, we found that removing the source resistance on the promise has no influence on signal quality, which can save BOM cost and has advantage for product cost.The resistance value of terminal ODT has been identified by pre-simulation, even before we began to design schematic and PCB layout.The traditional approach is: after PCB produced and sent back, based on the debug results of hardware and software to configure ODT resistance value. By doing this, we can reduce the debug time, finally we can reduce the total develop and research time cycle, which could improve the competitiveness of product.The thesis presents one unique method to decrease stub effect of vias crossing layers and the same time create one method to reduce diff pair impedance dismatch.(Having been authorized Patent.Patent No.: ZL201020167196.0).According to this topic’s research a design method for DDR3 in optical network is developed which can shorten the RD time cycle, reduce development cost and make products more competitive by identifying ODT resistance value in advance and removing source resistance.