The Research And Applications Of IBIS Model For EraSoc

As the incessant development in the manufacturing and processing technology of Integrated Circuits(IC) and Printed Circuit Board(PCB) industry in recent years, the speed of IC chips and electronic systems gets more and more fast, the areas smaller, the scale larger and the density higher. While this brings about convenience to customers, challenges face electronic engineers also come up. The issues of Signal Integrity, such as signal distortion, propagation delay and attenuation, have great influence on the performance and functionality of the target electronic systems. In order to solve the signal integrity problems, engineers have to account for the issues in every possible period, such as the planning, designing and debugging phase of the product. In this paper the way to find out and solve the problem using simulation method during the design period is studied and then applied on a development board of the erasoc-1000.After a brief description of the signal integrity problems in high speed circuit system, the signal integrity simulation environment for the board of the EraSoC was first set up: the IBIS model was first created for the chip. With this model, a preliminary analysis for the I/O buffer can be implemented and more detail and accurate signal integrity simulation become possible.The simulation and analysis were then done for the system board based on Erasoc-1000. The utilization of IBIS model can solve the stable problems of the Erasoc development board and remove an obstacle on the way to market for Erasoc, and is of great importance in both theory and implementation.