Study On The Jitter Testing Technology For Optical Communication Analyzer

Synchronous Digital Hierarchy (SDH) is featured by standardized rate of digital signal and frame structure and made an universal system applicable to optical fiber, microwave and satellite transmission in replacement of Plesiochronous Digital Hierarchy (PDH). The 0.172 standard of SDH series jitter and drifting measure equipments established by Telecommunication Standardization Sector (ITU-T) regulates that jitter refers to a short-term variation of digital signal in effective instantaneous deviation from ideal position of time. In SDH network, the jitter caused by tributary mapping and pointer adjustment results in error code and noise signal thereby affecting quality of communication. For a jitter measure instrument based on SDH, ITU-T requires that its main functions include jitter creation and measure.The research in this paper is mainly on key technologies of creation and measure of SDH jitter.Firstly, the paper introduces research background, significance and development trends of SDH jitter measure technologies in China and abroad, and analyzes the influence of SDH jitter of communication system.Secondly, according to proposals of ITU-T 0.172, the clock signal source with jitter is designed. Jitter signal is rated rectangular square wave and its source is sinusoidal jitter. Then, the creation algorithm of clock signal with jitter based on DDS technology is proposed. For restriction of FPGA hardware, the DDS-based jitter signal source can only produce low-frequency signal. Then, using modulation chip, the creation algorithm of high-intermediate frequency clock signal with jitter based on IQ modulation technology is proposed.Thirdly, according to the functional block diagram of the jitter measure instrument in ITU-T 0.172 proposal, a jitter measure circuit based on data transition and tracking loop is presented, which gives very good tracking performance under low SNR. After entering into locking status, when burst noise is added it can re-enter locking status quickly. The working principle of modules of jitter measure circuit is analyzed and the expression of jitter error range of single-phase jitter measurement is deduced, it is theoretically proved that jitter error range was inversely associated with plus of filter and directly related with the jitter frequency and extent. To improve accuracy and ease restriction of sampling frequency to accuracy, a jitter measure circuit based on multi-phase data transition and tracking loop is presented. The design principle of phase discriminator in multi-phase jitter measure circuit is analyzed in detail; 4-phase jitter error expression was deduced. Comparing to single-phase jitter error expression, measure accuracy is increased 4 times.At last, FPGA verification on designed algorithm is carried out. According to requirements of 0.172 standard, the single-phase jitter measure circuit on stratix chip by quartusⅡis implemented. Delay primitive in Xilinx was used to implement the multi-phase jitter measure circuit on virtex5 chip.