Physical Implementation Of Data-Driven Based Clock Gating Technique

In high-performance microprocessors and SoCs, clock tree power accounts for a large proportion of the total power consumption. Clock gating is an effective technique used for clock tree power saving. However, synthesis based clock gating still leaves a large amount of redundant clock pulses, resulting in low clock gating efficiency. Data-driven gating (DDCG) can effectively disable redundant clock pulses, improve gating efficiency and reduce clock tree power.Taking data driven clock gating technique as the research priority, this thesis groups registers whose switching vectors are highly correlated, and their physical locations are also considered. The register clustering process can be mathematically described as minimum cost perfect matching (MCPM) problem, mainly including three algorithms. First, adopting general graph's maximum weight matching algorithm to obtain the optimal clusters. Second, adopting state vector processing algorithm to obtain the number of clusters' redundant clock pulses, which is used to characterize toggling activity correlations of registers. Third, adopting minimum enclosing circle algorithm to characterize the impact of registers' coordinates. To reduce area overhead, three approches are proposed, including filtering the register clusters by gating efficiency, performing mix-sized clustering and XOR logic approximation.Based on SMIC 40nm LOGIC process technology, DDCG technique is firstly designed in benchmark circuits ISCAS89, and its application condition is discussed. Then the technique is tested and verified in DW8051 and Cortex-M3 circuits with detailed data analysis and comparison. Compared with synthesis based clock gating technique, clock tree power is reduced by 33.13% and 35.36% respectively when adopting the improved DDCG technique. Correspondingly, total power is reduced by 20.65% and 16.42%, and area overhead increases by 12.5% and 9.67%. Compared with the traditional DDCG technique, the improved DDCG technique reduces clock tree power by 17.01% and 31.92% respectively. Meanwhile, total power is reduced by 14.3% and 13.08% and area overhead is reduced by 11.41% and 11.74%.