Optimization And Design Of Clock Gating Based On DSP

The increasing demand for low power mobile computing and consumer electronics products has refocused DSP (Digital Signal Processor) design on lowering power and increasing energy efficiency. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. It is observed that the commonly used clock gating still leaves a large amount of redundant clock pulses.To disable these redundant clock pulses, this paper studies data-driven clock gating optimization based on synthesis and employs for FFs at the gate level, which is the most aggressive possible. Firstly, obtain the statistics from extensive simulations of typical modes of operation and statistical analysis of FFs toggling activity. Get preliminary preferred locations of FFs in the layout by running the placement tool. Then, FFs are grouped based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout. To maximize the power savings, the optimal gater fan-out is derived based on FFs toggling probalilities. The optimal FF grouping is implemented by repeating the MCPM algorithm to reduce the redundant clock pulses. Lastly, clock gating of data-driven FF grouping is implemented by XOR self-gating. The FFs Clustering methodology is adopted for timing closure. At the same time, this paper analyzes the impact on clock tree and standard cell utilization. Compared with synthesis-based clock gating, the total power saving is 13.81mW, reducing the power to 8.37%. The sequential power saving is 17.35mW, reducing the power to 29.15%.The data-driven clock gating is suitable for the most DSP core. And, data-driven clock gating is also useful for application-specific integrated circuit, if FFs have the characteristics of fixed activity and very low toggling rate.