Design Of Low-leakage Standard Cell Library In Near-Threshold Region

With the widespread application of battery powered devices and the scaling trends in CMOS technology,lower the supply voltage has been proved to be an effective approach towards lowering power consumption.The potential problem of the growing proportion of leakage power in the total power consumption is exposed by low power design,as well as the increasing sensitivity of digital circuits towards process variations.Therefore,leakage power has been treated as a great challenge of the design of the lower-power digital circuits nowadays.Based on the analysis of the physical sources of leakage power,this thesis reviews the existing leakage reduction techniques and optimizes the design of logic cells accordingly because the traditional structure based on the above-threshold degrades greatly in the near-threshold region,suffering from low performance or high leakage.In terms of the combinational logic cell,a new SSCMOS technique based on low-power design is adopted,which reduces the leakage current with the stacking effect.For design of sequential cells,a new structure is adopted based on self-super-cutoff effect without any additional control circuits or charge pump to reduce the leakage power.Additionally,the layout design of optimized cells is completed and the establishment of the library is accomplished.The design of standard cell library is completed and validated based on GF0.18?m,with the metrics including leakage power and delay.The validation is based on the synthesis and analysis of the test case of a real-time clock.The results show that compared with the original library,the proposed library has achieved an improvement of 13.4%in the reduction of leakage power,9.8%in the switch power reduction and 3.0%in the total power reduction.