Research Of Low Voltage SRAM Timing Circuit Technology

In recent years, the mobile Internet technology has been developing with high speed, which leads to a fact that the need of Static Random Access Memory (SRAM for short) for microprocessor and system on chip is more and more important. With the further development of scaling technique, supply voltage of chip is becoming lower. However, process variation is also increased, which will affect the performance of system. For example, it will increase the timing margin of SRAM timing control circuit, reduce the SRAM speed and increase the power consumption of SRAM. In order to solve this problem, timing control circuit of low voltage SRAM is researched in depth in this paper. The main work of this paper is as follows:Firstly, the circuit structure and working principle of SRAM is introduced. Then, the effect of timing optimization between inverter delay chain and traditional replica bit-line technique is compared. In addition, several novel techniques about replica bit-line, their principle and circuit structure are told in this paper, which are configurable replica bit-line technique, multi-stage replica bit-line technique, digitized replica bit-line delay technique, multiple-stage parallel replica bit-line delay addition technique and dual replica bit-line delay technique Furthermore, the results of Monte Carlo simulation of these techniques will be compared in different corner. At the same time, the weaknesses of these techniques will be analyzed.Finally, a novel replica bit-line technique named 8-transistor dual digitized replica bit-line delay technique is put forward in this paper, which will reduce timing variation of Sense Amplifier Enable Signal (SAE for short) for Static Random Access Memory. The proposed technique combines digitized replica bit-line delay technique and dual replica bit-line delay technique, which reduces the SAE variation to a very low level. At the same time, a novel 8-transistor replica cell is proposed. Compared with the traditional replica bit-line technique, when the supply voltage and temperature are respectively 0.7V and 125 degree Celsius, the SAE variation and cycle time of proposed technique is reduced 71.8% and 25.4% respectively in TSMC 65nm CMOS process and SS corner.