Design And Verification Of DDR2 Memory Controller Based On Dual-PLB-Slaves

With the rapid development of electronic technology, the needs of the electronics industry for memory is increasing, the memory performance requirements are also increasing. With efficient transmission rate, low-power, reliability and security advantages, DDR2 memory controller to become the best choice, widely used in general-purpose computers and high-end embedded systems. DDR2 memory controller is a control interface to achieve DDR2 memory access, its timing and structure is complex.By learning DDR2 memory technology and Core Connect bus specification and related technologies, in order to improve the performance of memory and increase memory bandwidth utilization, the paper proposes a dual-based PLB bus DDR2 memory controller design. This design of DDR2 memory controller compatible with international standards, full-featured. Its high design difficulty will provide a certain amount of experience to enhance the independent memory design.The main work focused on the key module DDR2 memory controller and dual PLB bus interface design, building functional verification platform and verify the implementation of verification coverage verification and other aspects. Firstly, with the advanced top-down design ideas, this paper use a hardware description language Verilog to achieve the DDR2 memory controller. It achieve a high rate of data transmission which is up to 333 MHz, and the bandwidth up to 5.32 GB / sec. Then through studying Core Connect bus, the use of PLB bus design with dual PLB bus interface make high bandwidth utilization up to 83%, while the interface can be configured as a single PLB depending on the application, this improved application flexibility. What's more, through learning the principle of functional verification and validation platform structure, build a DDR2 memory controller simulation platform, designed the platform for the bus functional model components and the functional verification testcase, completed the simulation of DDR2 memory controller based on bus functional model. Lastly, verify the coverage verification of functional simulation work, coverage is more than 90%, meeting the verification requirements.This article completes the DDR2 memory controller design, the key technology of the dual PLB bus interface has been studied and designed to improve the performance of the memory controller. Through building simulation platform and the corresponding functional model, the function of the memory controller were validated and functional verification and verification coverage analysis to ensure that the design is correct. Eventually,it achieve full functionality DDR2 memory controller based on the dual PLB bus interface.