Design And Verification Of The DDR3 Controller Based On CoreConnect

There is a large requirement of data memory in Electronic information industry. As the demand increasing, the memory devices have constantly made new replacements. Developing to the now, because DDR memory has a benefit of high-speed, high efficiency and low power, it will gradually replace the conventional memory device and become a mainstream in the market. DDR3 SDRAM is the third generation of DDR memory, it has inherited the basic functions of DDR and made more promotion on the performance comparing with DDR of last generations, so it will well meet the data storage requirements of PC systems and various SOC systems.Memory performance is the key factor which affects the system performance, while memory controller that designed to use also determines the actual memory performance. DDR3 SDRAM theoretically has a maximum transfer speeds of up to 1.6Gbps over, but in the practical application of users, the need for timing control for different user logic, it is difficult to achieve high bandwidth DDR memory utilization. So for the user to design a pretext to achieve user logic controllers and control logic speed matching is a reliable guarantee for DDR memory performance can be achieved.Firstly, the development and background of DDR SDRAM are brief analyzed, IBM's Core Connect bus protocols are studied, while the DDR, DDR2, DDR3 functional principles and working characteristics were studied in detail. Based on the above, to satisfy data transmission requirements of SOC embedded system, and to achieve high speed and efficiency, this paper described a scheme of DDR3 controller design using Core Connect interface which will meet the basic transfer requirements. The scheme introduces the basic functional structure of DDR3 controller and it analyzes the function of each module implementation and mainly describes the realization of data pipe transmission and MC module. Meanwhile, with realizing the basic function of DDR, it is more deeply studied that how user interface logic is optimized to improve the efficiency of the controller. Finally, the verification methods of DDR3 controller to perform systematic function simulation and verification are introduced, including block-level verification, virtual platform verification and FPGA verification methods, which include building DDR3 controller simulation platform, creating valid verification cases and test results judgment analysis.