DDR2 SDRAM Memory Interface Based On Spartan-3 FPGA

The inner memory is in charge of the data transfer,storage and read/write in the computer system, as one of the three most important parts of the computer system (the other two are main-board and CPU), it plays great role in computer systems. Allegorically the inner memory is the"big storehouse"of the CPU data processing, all the instructions and data processed by CPU must be transferred by inner memory to the other parts of computer system. So that the performance of the inner memory will heavily impact the stability and running performance of computer system.In current electronics system designing, inner memory is used more and more broadly, meanwhile we are expecting more and more from the inner memory. It's required to be read/written more quickly, larger in capacity and lower cost as the marketing competent is more and more tight, while keeping the same or seeking higher performance. With this trend, the design and implementation of inner memory with large capacity and high speed are very important. In recent years, the inner memory products evolved from small capacity to big capacity, from low speed to high speed. From the technology point of view, it evolved from DRAM to SDRAM and then DDR SDRAM and DDR2 SDRAM. Compared with the normal SDRAM, the interface design of DDR2 SDRAM is much more complicated as the capacity and speed are increased significantly. On the one hand, as the I/O module resource is limited, the data multiplex and clock transferring must be implemented in the core logic bank of FPGA, the designer have to draw schematic by hand to ensure critical clock scheduling for the interface. On the other hand, we have to pay much attention to the time clock issues (including temperature and voltage compensation) related to the DDR2 interface. To implementing the DDR2 interface correctly, much careful work is needed and the compatibility design is needed to ensure the performance and stability of the system.The thesis is the implementation of DDR2 memory interface based on Spartan-3 FPGA of Xilinx corporation. Xilinx FPGA provides I/O blocks and logic resources that make the interface design easier and more reliable. The I/O blocks, along with the logic modules are configured, verified, implemented and properly connected to FPGA in the RTL code, carefully simulated and then verified in hardware to ensure a reliable memory interface system.