Design And FPGA Implementation Of DDR2 Controller IP

DDR2 SDRAM is the dominant mainstream system memory product in the DRAM market today. In addition to general computer systems, a large number of embedded systems using DDR2 memory have been introduced. The number of SoCs integrated with DDR2 interface module is growing. As a result, to de-sign a memory controller matching DDR2 SDRAM will have great application prospects.Based on the characteristics of DDR2 SDRAM and the research of existing DDR2 SDRAM controller, this paper builds the overall architecture of DDR2 controller. Then, with top-down and modular design methods, the DDR2 con-troller is split into a number of modules. Finally, the initialization module, config-ure module, execute module and data channels module of DDR2 SDRAM controller are designed with Verilog HDL language. According to the problem encountered in the design process, the overall architecture is improved. An interface between the DDR2 controller and Altera digital PHY is designed,based on the analysis the performance of Altera digital PHY. We build a DDR2 SDRAM controller simulation and verification platform. The designed modules are simulated. The FPGA Demo of the basic read / write operations to DDR2 SDRAM is implemented on Altera Stratix II GX 90 evaluation board.The main features of designed DDR2 controller are as follows:1. Support digital PHY circuit. No actual hardware circuits needed be-tween the DDR2 controller and DDR2 SDRAM. This can save the cost of design and reducing the size of the hardware circuit.2. Split the configure port from the initialization module. As a result, the operations are simplified.3. Support multiple DDR2 memory chips, making the application range of the DDR2 controller broader.4. Support the three new technology of DDR2, exerting the identity of DDR2 memory deeply.5. Automatic refresh control of DDR2, providing the user-friendly con-trol of DDR2 memory.