Design Of Verification Platform For Direct Memory Access Controller Based On UVM

With the increasing complexity of chip functions and the continuous evolution of advanced process nodes,the design of chip systems is becoming increasingly complex,and the importance of the verification process in the chip design process continues to increase.Verification is also becoming more and more complex during the design process,and the percentage of the entire chip development cycle it takes is also increasing.Efficient while ensuring completeness is the challenge facing the current verification process.This topic originates from the DMA controller module verification project in which the author participated in the internship company.The goal is to build a DMA controller verification platform.By using UVM,the platform has better reusability and can complete the expected verification work efficiently and fully.Compared with the advantages of traditional verification methods,the verification process of universal verification methodologies is more random and has improved efficiency.It can effectively find defects in design and has strong practical significance.The object of this verification is the DMA controller mounted on the AHB bus.Its function is to provide high-speed data transmission between the memory and peripheral devices,or between the memories.Use UVM based on System Verilog language to build a complete verification platform for functional verification of research objects.The specific research results are as follows: The development process of the verification language and methodology is studied,the characteristics and advantages of the widely used universal verification methodology are understood,and the structure and related mechanisms of the verification environment of the universal verification methodology are mastered.And complete a detailed analysis of the DMA controller module to understand its functions in the system and detailed working methods and configuration information.Based on the characteristics of the DMA controller not only acting as a master but also a slave in the system,this article extracts detailed functional verification points to ensure the completeness of the verification.Including the arbitration results of the priorities between different channels,different triggering modes of transmission requests,the length of burst transmissions,and the different pointer rotation modes of the source and destination.Completed the design of the verification platform for the DMA controller,including the reference model,register model,scoreboard and other components.Use the factory mechanism,phase mechanism,and sequence mechanism included in the universal verification methodology to develop,for example,to complete the component instance and the interconnection between components in different phases,and the realization of the main function of each component.The method of the instance is through The factory mechanism ensures the automatic operation of the internal phase of each component and enables the component to be overloaded.The use of a sequence mechanism makes the generation and driving of incentives independent,which greatly improves the reusability of the verification environment.AHB?VIP is added to the verification platform to implement the drive of incentives and the inspection of related protocols.Based on the transaction-level transmission mode modeling and verification platform,a randomization strategy with constraints is used for simulation verification.Functional coverage points and related test cases are written according to the characteristics of the verification object.The platform is started for simulation verification and experimental data is collected.Completed the analysis of the knot simulation results,which mainly include code coverage and function coverage.The final result has a functional coverage of 100% and a code coverage of more than 90%,and analyzes the uncovered parts to ensure its rationality.